source: docs/HPCA2012/10-related.tex @ 4448

Last change on this file since 4448 was 1693, checked in by lindanl, 8 years ago

Minor changes.

File size: 2.4 KB
1\section{Related Work}
4There has been work in the past which has sought to address the
5overheads of text processing in specific applications (e.g., XML
6parsers) and have adopted specialized hardware and software solutions
7for each application.
8% Event-based SAX (Simple API for XML) parsers avoid the tree
9% construction costs of the more flexible DOM (Document Object Model)
10% parsers \cite{Perkins05}.
11Nicola and John specifically identified the traditional method of XML
12parsing as a threat to database performance and outlined a number of
13potential directions for improving performance \cite{NicolaJohn03}.
14The commercial importance of XML parsing has spurred the development
15of numerous multi-threaded and hardware-based approaches:
16Multithreaded XML techniques include preparsing the XML file to locate
17key partitioning points~\cite{ParaDOM2009,LiWangLiuLi2009} and
18speculative p-DFAs~\cite{ZhangPanChiu09}. Hardware methods include
19custom XML chips \cite{Leventhal2009} and FPGA-based implementations
20\cite{DaiNiZhu2010}.  Intel's SSE4 instructions targeted
21XML parsers, but these have not seen widespread use because of portability
22concerns and the programming challenges that accompany low level
23instructions~\cite{sse4}. Recently, Cameron et
24al.~\cite{CameronHerdyLin2008, cameron-EuroPar2011} designed an
25accelerated XML parser using widely available SSE2 instructions
26and proposed an inductive doubling instruction set ~\cite{CameronLin2009},
27by which the performance can further improved.
28Finally, others have explored the design of custom
29hardware for bit parallel operations for text search in network
34% To accelerate XML parsingmost of the recent work has
35% focused on parallelization through the use of multicore parallelism
36% for chip multiprocessors \cite{ZhangPanChiu09, },
39% In this paper, we have introduce parallel bit streams as a general
40% abstraction to parallelize and improve the performance general text
41% processing. We have developed a compiler tool chain and the runtime to
42% enable bit streams to exploit SIMD extensions found on commodity
43% processors.  We are also the first to perform a detailed analysis of
44% SIMD instruction extensions across three generations of Intel
45% processors including the new 256-bit AVX extensions. Finally, we have
46% shown the benefits of using multithreading in conjunction with data
47% parallel phases of the application.
Note: See TracBrowser for help on using the repository browser.