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13% Author:       Paul C. Anagnostopoulos
14%               Windfall Software
15%               978 371-2316
16%               paul@windfall.com
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23\documentclass{sigplanconf}
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32\usepackage{amsmath}
33\usepackage{pgfplots}
34
35\begin{document}
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41\conferenceinfo{PPoPP 2014}{February 15-19, 2013, Orland, Florida, United States} 
42\copyrightyear{2013} 
43\copyrightdata{978-1-nnnn-nnnn-n/yy/mm} 
44\doi{nnnnnnn.nnnnnnn}
45
46% Uncomment one of the following two, if you are not going for the
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53                                  % (paid open-access papers,
54                                  % short abstracts)
55
56\titlebanner{banner above paper title}        % These are ignored unless
57\preprintfooter{short description of paper}   % 'preprint' option specified.
58
59\title{Bitwise Data Parallelism in Regular Expression Matching}
60\subtitle{Subtitle Text, if any}
61
62\authorinfo{Robert D. Cameron \and Kenneth S. Herdy \and Dan Lin \and Meng Lin \and Ben Hull \and Thomas S. Shermer \and Arrvindh Shriraman}
63           {Simon Fraser University}
64           {\{cameron,ksherdy,lindanl,linmengl,bhull,shermer,ashriram\}@cs.sfu.ca}
65
66\maketitle
67
68\begin{abstract}
69\input{abstract}
70\end{abstract}
71\category{Theory of computation}{Formal languages and automata theory}{Regular languages}
72\category{Computer systems organization}{Parallel architectures}{Single instruction, multiple data}
73
74% general terms are not compulsory anymore,
75% you may leave them out
76%\terms
77%term1, term2
78
79\keywords
80regular expression matching, grep, parallel bit stream technology
81
82\section{Introduction}
83
84The use of regular expressions to search texts for occurrences
85of string patterns has a long history and
86remains a pervasive technique throughout computing applications today.
87% {\em a brief history}
88The origins of regular expression matching date back to automata theory
89developed by Kleene in the 1950s \cite{kleene1951}.
90Thompson \cite{thompson1968} is credited with the first construction to convert regular expressions
91to nondeterministic finite automata (NFA).
92Following Thompson's approach, a regular expression of length m is first converted
93to an NFA with O(m) nodes. It is then possible to search a text of length n using the
94NFA in worst case O(mn) time. Often, a more efficient choice
95is to convert the NFA into a DFA. A DFA has only a single active state at any time
96in the matching process and
97hence it is possible to search a text at of length n in worst-case O(n) optimal.
98However, it is well known that the conversion of an NFA to an equivalent DFA may result
99in state explosion. That is, the number of resultant DFA states may increase exponentially.
100In \cite{Baeza-yates_anew} a new approach to text searching was proposed based on bit-parallelism \cite{baeza1992new}.
101This technique takes advantage of the intrinsic parallelism of bitwise operations
102within a computer word. Given a w-bit word, the Shift-Or algorithm \cite{Baeza-yates_anew} algorithm uses the
103bit-parallel approach to
104simulate an NFA in O($nm/w$) worst-case time.
105
106A disadvantage of the bit-parallel Shift-Or pattern matching approach
107in comparison to simple string matching algorithms is an inability to skip input characters.
108For example, the Boyer-Moore family of algorithms \cite{boyer1977fast} skip input characters
109to achieve sublinear times in the average case. Backward Dawg Matching
110(BDM) string matching algorithms \cite{crochemore1994text} based on suffix automata are able to skip characters.
111The Backward Nondeterministic Dawg Matching (BNDM) pattern matching algorithm \cite{wu1992fast} 
112combines the bit-parallel advantages of Shift-Or and with the character skipping advantages of the BDM algorithm.
113The nrgrep pattern matching tool is built over the BNDM algorithm,
114and hence the name nrgrep \cite{navarro2000}.
115
116{\em a brief review} 
117There has been considerable interest in using parallelization techniques
118to improve the performance of regular expression matching on parallel hardware
119such as multi-core processors (CPUs), graphics processing units (GPUs),
120field-programmable gate arrays (FPGAs), and even more exotic architectures such as
121the Cell Broadband Engine (Cell BE). % FPGA results (synthesis of patterns into logic circuits) vs. memory based approaches (STTs in memory)
122%CPU
123Scarpazza and Braudaway \cite{scarpazza2008fast} demonstrated that
124text processing algorithms that exhibit irregular memory access patterns
125can be efficiently executed on multicore hardware.
126In related work, Pasetto et al. presented a flexible tool that
127performs small-ruleset regular expression matching at a rate of
1282.88 Gbps per chip on Intel Xeon E5472 hardware \cite{pasetto2010}.
129Naghmouchi et al. demonstrated that the Aho-Corasick (AC)
130string matching algorithm \cite{aho1975} is well suited for parallel
131implementation on multi-core CPUs, GPUs and the Cell BE \cite{scarpazza2011top, naghmouchi2010}.
132On each hardware, both thread-level parallelism (additional cores) and data-level parallelism
133(wide SIMD units) are leveraged for performance.
134Salapura et. al., advocated the use of vector-style processing for regular expressions
135in business analytics applications and leveraged the SIMD hardware available
136on multi-core processors to acheive a speedup of better than 1.8 over a
137range of data sizes of interest \cite{salapura2012accelerating}.
138%Cell
139In \cite{scarpazza2008}, Scarpazza and Russell presented a SIMD tokenizer
140that delivered 1.00–1.78 Gbps on a single
141Cell BE chip and extended this approach for emulation on the Intel Larrabee
142instruction set \cite{scarpazza2009larrabee}.
143On the Cell BE, Scarpazza \cite{scarpazza2009cell} described a pattern matching
144implementation that delivered a throughput of 40
145Gbps for a small dictionary of approximately 100 patterns, and a throughput of 3.3-3.4
146Gbps for a larger dictionary of thousands of patterns. Iorio and van Lunteren \cite{iorio2008} 
147presented a string matching implementation for automata that achieves
1484 Gbps on the Cell BE.
149% GPU
150In more recent work, Tumeo et al. \cite{tumeo2010efficient} presented a chunk-based
151implementation of the AC algorithm for
152accelerating string matching on GPUs. Lin et al., proposed
153the Parallel Failureless Aho-Corasick (PFAC)
154algorithm to accelerate pattern matching on GPU hardware and
155achieved 143 Gbps throughput, 14.74 times faster
156than the AC algorithm performed on a four core
157multi-core processor using OpenMP \cite{lin2013accelerating}.
158
159Whereas the existing approaches to parallelization have been
160based on adapting traditional sequential algorithms to emergent
161parallel architectures, we introduce both a new algorithmic
162approach and its implementation on SIMD and GPU architectures.
163This approach relies on a bitwise data parallel view of text
164streams as well as a surprising use of addition to match
165runs of characters in a single step.  The closest previous
166work is that underlying bit-parallel XML parsing using 128-bit SSE2 SIMD
167technology together with a parallel scanning primitive also
168based on addition \cite{cameron2011parallel}.   
169However, in contrast to the deterministic, longest-match
170scanning associated with the ScanThru primitive of that
171work, we introduce here a new primitive MatchStar
172that can be used in full generality for nondeterministic
173regular expression matching.   We also introduce a long-stream
174addition technique involving a further application of MatchStar
175that enables us to scale the technique to $n$-bit addition
176in $\lceil\log_{64}{n}\rceil$ steps.   We ultimately apply this technique,
177for example, to perform
178synchronized 4096-bit addition on GPU warps of 64 threads.
179
180There is also a strong keyword match between the bit-parallel
181data streams used in our approach and the bit-parallelism
182used for NFA state transitions in the classical algorithms of
183Wu and Manber \cite{wu1992agrep}, Baez-Yates and Gonnet \cite{baeza1992new}
184and Navarro and Raffinot \cite{navarro1998bit}.
185However those algorithms use bit-parallelism in a fundamentally
186different way: representing all possible current NFA states
187as a bit vector and performing parallel transitions to a new
188set of states using table lookups and bitwise logic.    Whereas
189our approach can match multiple characters per step, bit-parallel
190NFA algorithms proceed through the input one byte at a time.
191Nevertheless, the agrep \cite{wu1992agrep} and
192nrgrep \cite{navarro2000} programs implemented using these techniques remain
193among the strongest competitors in regular expression matching
194performance, so we include them in our comparative evaluation.
195
196The remainder of this paper is organized as follows.
197Section \ref{sec:grep} briefly describes regular expression
198notation and the grep problem.
199Section \ref{sec:bitwise} presents our basic algorithm and MatchStar
200using a model of arbitrary-length bit-parallel data streams.
201Section \ref{sec:blockwise} discusses the block-by-block
202implementation of our techniques including the long stream
203addition techniques for 256-bit addition with AVX2 and
2044096-bit additions with GPGPU SIMT.
205Section \ref{sec:analysis} 
206Section \ref{sec:SSE2} 
207Section \ref{sec:AVX2} 
208Section \ref{sec:GPU} 
209Section \ref{sec:Concl} concludes the paper with a discussion of areas for future work.
210
211\section{Regular Expression Notation and Grep}\label{sec:grep}
212
213We follow common Posix notation for regular expressions.
214A regular expression specifies a set of strings through
215a pattern notation.   Individual characters normally
216stand for themselves, unless they are one of the
217special characters \verb:*+?[{\(|^$.: that serve as metacharacters
218of the notation system.  Thus the regular expression \verb:cat:
219is a pattern for the set consisting of the single 3-character
220string ``\verb:cat:''.   The special characters must be escaped
221with a backslash to prevent interpretation as metacharacter, thus
222\verb:\$: represents the dollar-sign and \verb:\\\\: represent
223the string consisting of two backslash characters.
224Character class bracket expressions are pattern elements
225that allow any character in a given class to be used in a particular
226context.  For example, \verb:[@#%]: is a regular expression
227that stands for any of the three given symbols.  Contiguous
228ranges of characters may be specified using hyphens;
229for example \verb:[0-9]: for digits and \verb:[A-Za-z0-9_]:
230for any alphanumeric character or underscore.  If the
231caret character immediately follows the opening bracket,
232the class is negated, thus \verb:[^0-9]: stands for
233any character except a digit.  The period metacharacter
234\verb:.: stands for the class of all characters.
235
236Consecutive pattern elements stand for strings formed by
237concatenation, thus \verb:[cd][ao][tg]: stands for the
238set of 8 three-letter strings ``\verb:cat:'' through ``\verb:dog:''.
239The alternation operator \verb:|: allows a pattern to be
240defined to have to alternative forms, thus \verb:cat|dog:
241matches either ``\verb:cat:'' or ``\verb:dog:''.  Concatenation
242takes precedence over alternation, but parenthesis may be
243used to change this, thus \verb:(ab|cd)[0-9]: stands for any
244digit following one of the two prefixes  ``\verb:ab:'' or ``\verb:cd:''.
245
246Repetition operators may be appended to a pattern to specify
247a variable number of occurrences of that pattern. 
248The Kleene \verb:*: specifies zero-or-more occurrences
249matching the previous pattern, while \verb:+: specifies one-or
250more occurrences.  Thus \verb:[a-z][a-z]*: and \verb:[a-z]+:
251both specify the same set: strings of at least one lower-case
252letter.  The postfix operator \verb:?: specifies an optional
253component, i.e., zero-or-one occurrence of strings matching
254the element.  Specific bounds may be given within braces:
255\verb:(ab){3}: specifies the string ``\verb:ababab:'',
256\verb:[0-9A-Fa-f]{2,4}: specifies strings of two, three
257or four hexadecimal digits, and \verb:[A-Z]{4,}: specifies
258strings of at least 4 consecutive capital letters.
259
260The grep program searches a file for lines containing matches
261to a regular expression using any of the above notations.
262In addition, the pattern elements \verb:^: and \verb:$:
263may be used to match respectively the beginning or the
264end of a line.  In line-based tools such as grep, \verb:.:
265matches any character except newlines; matches cannot extend
266over lines.
267Normally, grep prints all matching
268lines to its output.  However, grep programs typically
269allow a command line flag such as \verb:-c: to specify
270that only a count of matching lines be produced; we use
271this option in our experimental evaluation to focus
272our comparisons on the performance of the underlying matching
273algorithms.
274
275\section{Matching with Bit-Parallel Data Streams}\label{sec:bitwise}
276
277Whereas the traditional approaches to regular expression matching
278using NFAs, DFAs or backtracking all rely on a byte-at-a-time
279processing model, the approach  we introduce in this paper is based
280on quite a different concept:  a data-parallel approach to simultaneous
281processing of data stream elements.  Indeed, our most abstract model
282is that of unbounded data parallelism: processing all elements of
283the input data stream simultaneously.   In essence, we view
284data streams as (very large) integers.   The fundamental operations
285we apply are based on bitwise logic and long-stream addition.
286
287Depending on the available parallel processing resources, an actual
288implementation may divide an input stream into blocks  and process
289the blocks sequentially.   Within each block  all elements of the
290input stream are processed together, relying the availability of
291bitwise logic and addition scaled to the block size.   On commodity
292Intel and AMD processors with 128-bit SIMD capabilities (SSE2),
293we typically process input streams 128 bytes at a time.   In this
294case, we rely on the Parabix tool chain \cite{lin2012parabix}
295to handle the details of compilation to block-by-block processing.
296As we show later, however, we have also adapted Parabix technology to processing
297blocks of 4K bytes at time in our GPGPU implementation,
298relying on the application of our long-stream addition technique
299to perform 4096-bit additions using 64 threads working in lock-step
300SIMT fashion each on 64-bit processors.
301
302A key concept in this streaming approach is the derivation of bit streams
303that are parallel to the input data stream, i.e., in one-to-one
304correspondence with the data element positions of the input
305streams.   Typically, the input stream is a byte stream comprising
306the 8-bit character code units of a particular encoding such
307as extended ASCII, ISO-8859-1 or UTF-8.   However, the method may also
308easily be used with wider code units such as the 16-bit code units of
309UTF-16.   In the case of a byte stream, the first step is to transpose
310the byte stream into eight parallel bit streams, such that bit stream
311$i$ comprises the $i^\text{th}$ bit of each byte.   These streams form
312a set of basis bit streams from which many other parallel bit
313streams can be calculated, such as character class bit
314streams such that each bit $j$ of the stream specifies
315whether character $j$ of the input stream is in the class
316or not.  Figure \ref{fig:streams} shows an example of an
317input byte stream in ASCII, the eight basis bit streams of the
318transposed representation, and several character class bit streams
319that may be computed from the basis bit streams using bitwise logic.
320Transposition and character class construction are straightforward
321using the Parabix tool chain \cite{lin2012parabix}.
322
323\paragraph*{Marker Streams.}  Now consider how bit-parallel data
324streams can be used in regular expression matching.   Consider
325the problem of searching the input stream of Figure \ref{fig:streams}
326to finding occurrence of strings matching
327the regular expression \verb:a[0-9]*z:.
328The matching process involves the concept of {\em marker streams}, that
329is streams that mark the positions of current matches during the
330overall process.  In this case there are three marker streams computed
331during the match process, namely,
332$M_1$ representing match positions after an initial \verb:a:
333character has been found, $M_2$ representing positions
334reachable from positions marked by $M_1$ by further matching zero or
335more digits (\verb:[0-9]*:) and finally $M_3$ the stream
336marking positions after a final \verb:z: has been found.
337Without describing the details of how these streams are computed
338for the time being, Figure \ref{fig:streams} shows what each
339of these streams should be for our example matching problem.
340Note our convention that a marker stream contains a 1 bit
341at the next character position to be matched, that is,
342immediately past the last position that was matched.
343
344
345\paragraph*{MatchStar.}
346MatchStar takes a marker bitstream and a character class bitstream as input.  It returns all positions that can be reached by advancing the marker bitstream zero or more times through the character class bitstream.
347
348Figure \ref{fig:matchstar} illustrates the MatchStar method.  The second and third rows are the input bitstreams: the initial marker position bitstream and the character class bitstream derived from the source data.
349
350In the first operation ($T_0$), marker positions that cannot be advanced are temporarily removed from consideration by masking off marker positions that aren't character class positions using bitwise logic.  Next, the temporary marker bitstream is added to the character class bitstream.  $T_1$ has 1s in three types of positions.  There will be a 1 immediately following a block of character class positions that spanned one or more marker positions, at any character class positions that weren't affected by the addition (and are not part of the desired output), and at any marker position that wasn't the first in its block of character class positions.  Any character class positions that have a 0 in $T_1$ were affected by the addition and are part of the desired output.  These positions are obtained and the undesired 1 bits are removed by XORing with the character class stream. $T_2$ is now only missing marker positions that were removed in the first step as well as marker positions that were 1s in $T_1$.  The
351output marker stream is obtained by ORing $T_2$ with the initial marker stream.
352
353\begin{figure*}[tbh]
354\begin{center}
355\begin{tabular}{cr}\\
356source data & \verb`--142578---125-231-----127--5394---94761205-`\\
357$M_0$ & \verb`.......1......1..1..1...1.............1..1..`\\
358$D = $\verb:[0-9]: & \verb`..111111...111.111.....111..1111...11111111.`\\
359$T_0 = M_0 \wedge D$ & \verb`.......1.........1......1.............1..1..`\\
360$T_1 = T_0 + D$ & \verb`.1.........1111.......1..1..1111..1...1...1.`\\
361$T_2 = T_1 \oplus D$ & \verb`.1111111......1111....111.........1111.111..`\\
362$M_1 = T_2 \, | \, M_0$ & \verb`.1111111......1111..1.111.........11111111..`
363\end{tabular}
364
365\end{center}
366\caption{Match Star}
367\label{fig:matchstar1}
368\end{figure*}
369
370
371In general, given a marker stream $M$ and a character class stream $C$,
372the operation of MatchStar is defined by the following equation. 
373\[\text{MatchStar}(M, C) = (((M \wedge C) + C)  \oplus C) | M\]
374Given a set of initial marker positions, the result stream marks
375all possible positions that can be reached by 0 or more occurrences
376of characters in class $C$ from each position in $M$
377
378
379
380
381\section{Block-at-a-Time Processing}\label{sec:blockwise}
382
383The unbounded stream model of the previous section must of course
384be translated an implementation that proceeds block-at-a-time for
385realistic application.  In this, we primarily rely on the Pablo
386compiler of the Parabix toolchain \cite{lin2012parabix}.  Given input
387statements expressed as arbitrary-length bitstream equations, Pablo
388produces block-at-a-time C++ code that initializes and maintains all the necessary
389carry bits for each of the additions and shifts involved in the
390bitstream calculations.   
391
392In the present work, our principal contribution to the block-at-a-time
393model is the technique of long-stream addition described below.
394Otherwise, we were able to use Pablo directly in compiling our
395SSE2 and AVX2 implementations.   Our GPU implementation required
396some scripting to modify the output of the Pablo compiler for our
397purpose.
398
399\paragraph*{Long-Stream Addition.}  The maximum word size for
400addition on commodity processors is typically 64 bits.  In order
401to implement long-stream addition for block sizes of 256 or larger,
402a method for propagating carries through the individual stages of
40364-bit addition is required.  However, the normal technique of
404sequential addition using add-with-carry instructions, for example,
405is far from ideal.
406
407We have developed a technique using SIMD or SIMT methods for constant-time
408long-stream addition up to 4096 bits.   
409We assume the availability of the following SIMD/SIMT operations
410operating on vectors of $f$ 64-bit fields.
411\begin{itemize}
412\item \verb#simd<64>::add(X, Y)#: vertical SIMD addition of corresponding 64-bit fields
413in two vectors to produce a result vector of $f$ 64-bit fields.
414\item  \verb#simd<64>::eq(X, -1)# :  comparison of the 64-bit fields
415of \verb:x: each with the constant value -1 (all bits 1), producing
416an $f$-bit mask value,
417\item  \verb#hsimd<64>::mask(X)# : gathering the high bit of each 64-bit
418field into a single compressed $f$-bit mask value, and
419\item normal bitwise logic operations on $f$-bit masks.
420\item  \verb#simd<64>::spread(x)# : distributing the bits of
421an $f$ bit mask, one bit each to the $f$ 64-bit fields of a vector, and
422\end{itemize}
423
424Given these operations, our method for long stream addition of
425two $f \times 64$ bit values \verb:X: and \verb:Y: is the following.
426\begin{enumerate}
427\item Form the vector of 64-bit sums of \verb:x: and \verb:y:.
428\[\text{\tt R} = \text{\tt simd<64>::add(X, Y)} \]
429
430\item Extract the $f$-bit masks of \verb:X:, \verb:Y: and \verb:R:.
431\[\text{\tt x} = \text{\tt hsimd<64>::mask(X)} \]
432\[\text{\tt y} = \text{\tt hsimd<64>::mask(Y)} \]
433\[\text{\tt r} = \text{\tt hsimd<64>::mask(R)} \]
434
435\item Compute an $f$-bit mask of carries generated for each of the
43664-bit additions of \verb:X: and \verb:Y:.
437\[\text{\tt c} = (\text{\tt x} \wedge \text{\tt y}) \vee ((\text{\tt x} \vee \text{\tt y}) \wedge \neg \text{\tt r})\]
438
439\item Compute an $f$-bit mask of all fields of {\tt R} that will overflow with
440an incoming carry bit.  This is the {\em bubble mask}.
441\[\text{\tt b} = \text{\tt simd<64>::eq(R, -1)}\]
442
443\item Determine an $f$-bit mask identifying the fields of {\tt R} that need to be
444incremented to produce the final sum.  Here we find a new application of
445MatchStar!
446\[\text{\tt i} = \text{\tt MatchStar(c*2, b)}\]
447
448This is the key step.  The mask {\tt c} of outgoing carries must be
449shifted one position ({\tt c*2}) so that each outgoing carry bit becomes associated
450with the next digit.  At the incoming position, the carry will
451increment the 64-bit digit.   However, if this digit is all ones (as
452signalled by the corresponding bit of bubble mask {\tt b}, then the addition
453will generate another carry.  In fact, if there is a sequence of
454digits that are all ones, then the carry must bubble through
455each of them.   This is just MatchStar!
456
457\item Compute the final result {\tt Z}.
458\[\text{\tt Z} = \text{\tt simd<64>::add(R, simd<64>::spread(i))}\]
459
460\end{enumerate}
461\begin{figure}
462\begin{center}
463\begin{tabular}{c||r|r|r|r|r|r|r|r||}\cline{2-9}
464{\tt X} & {\tt 19} & {\tt 31} & {\tt BA} & {\tt 4C} & {\tt 3D} & {\tt 45} & {\tt 21} & {\tt F1} \\ \cline{2-9}
465{\tt Y} & {\tt 22} & {\tt 12} & {\tt 45} & {\tt B3} & {\tt E2} & {\tt 16} & {\tt 17} & {\tt 36} \\ \cline{2-9}
466{\tt R} & {\tt 3B} & {\tt 43} & {\tt FF} & {\tt FF} & {\tt 1F} & {\tt 5B} & {\tt 38} & {\tt 27} \\ \cline{2-9}
467{\tt x} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} \\ \cline{2-9}
468{\tt y} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
469{\tt r} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
470{\tt c} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} \\ \cline{2-9}
471{\tt c*2} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} \\ \cline{2-9}
472{\tt b} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
473{\tt i} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} \\ \cline{2-9}
474{\tt Z} & {\tt 3B} & {\tt 44} & {\tt 0} & {\tt 0} & {\tt 1F} & {\tt 5B} & {\tt 39} & {\tt 27} \\ \cline{2-9}
475\end{tabular}
476\end{center}
477\caption{Long Stream Addition}\label{fig:longadd}
478\end{figure}
479
480Figure \ref{fig:longadd} illustrates the process.  In the figure,
481we illustrate the process with 8-bit fields rather than 64-bit fields
482and show all field values in hexadecimal notation.  Note that
483two of the individual 8-bit additions produce carries, while two
484others produce {\tt FF} values that generate bubble bits.  The
485net result is that four of the original 8-bit sums must be
486incremented to produce the long stream result.
487
488A slight extension to the process produces a long-stream full adder
489that can be used in chained addition.  In this case, the
490adder must take an additional carry-in bit
491{\tt p} and produce a carry-out bit {\tt q}.
492This may be accomplished by incorporating {\tt p}
493in calculating the increment mask in the low bit position,
494and then extracting the carry-out {\tt q} from the high bit position.
495\[\text{\tt i} = \text{\tt MatchStar(c*2+p, b)}\]
496\[\text{\tt q} = \text{\tt i >> f}\]
497
498As described subsequently, we use a two-level long-stream addition technique
499in both our AVX2 and GPU implementations.  In principle, one can extend
500the technique to additional levels.  Using 64-bit adders throughout,
501$\lceil\log_{64}{n}\rceil$ steps are needed for $n$-bit addition.
502A three-level scheme could coordinate
50364 groups each performing 4096-bit long additions in a two-level structure.
504However, whether there are reasonable architectures that can support fine-grained
505SIMT style coordinate at this level is an open question.
506
507Using the methods outlined, it is quite conceivable that instruction
508set extensions to support long-stream addition could be added for
509future SIMD and GPU processors.   Given the fundamental nature
510of addition as a primitive and its novel application to regular
511expression matching as shown herein, it seems reasonable to expect
512such instructions to become available.
513\raggedbottom
514\section{Analytical Comparison with DFA and NFA Implementations}\label{sec:analysis}
515
516\begin{enumerate}
517\item Operations
518\item Memory behaviour per input byte: note tables of DFA/NFA.
519
520Bille and Throup \em{Faster regular expression matching}\cite{bille2009faster}
521
522\end{enumerate}
523
524
525
526\section{Commodity SIMD Implementation and Experimental Evaluation}\label{sec:SSE2}
527
528
529\subsection{Implementation Notes}
530\subsection{Evaluation Methodology}
531\subsection{Comparison}
532\begin{figure}
533\begin{center}
534\begin{tikzpicture}
535\begin{axis}[
536xtick=data,
537ylabel=Cycles per Byte,
538xticklabels={@,Date,Email,URIorEmail,xquote},
539tick label style={font=\tiny},
540enlargelimits=0.15,
541legend style={at={(0.5,-0.15)},
542anchor=north,legend columns=-1},
543ymax=8,
544ybar,
545bar width=7pt,
546]
547\addplot
548file {data/cycles1.dat};
549\addplot
550file {data/cycles2.dat};
551\addplot
552file {data/cycles3.dat};
553 
554\legend{Bitstreams,NRGrep,Grep,Annot}
555\end{axis}
556\end{tikzpicture}
557\end{center}
558\caption{Cycles per Byte}
559\end{figure}
560 
561\begin{figure}
562\begin{center}
563\begin{tikzpicture}
564\begin{axis}[
565xtick=data,
566ylabel=Instructions per Byte,
567xticklabels={@,Date,Email,URIorEmail,xquote},
568tick label style={font=\tiny},
569enlargelimits=0.15,
570legend style={at={(0.5,-0.15)},
571anchor=north,legend columns=-1},
572ymax=16,
573ybar,
574bar width=7pt,
575]
576\addplot
577file {data/instructions1.dat};
578\addplot
579file {data/instructions2.dat};
580\addplot
581file {data/instructions3.dat};
582 
583\legend{Bitstreams,NRGrep,Grep,Annot}
584\end{axis}
585\end{tikzpicture}
586\end{center}
587\caption{Instructions per Byte}
588\end{figure}
589
590\begin{figure}
591\begin{center}
592\begin{tikzpicture}
593\begin{axis}[
594xtick=data,
595ylabel=Instructions per Cycle,
596xticklabels={@,Date,Email,URIorEmail,xquote},
597tick label style={font=\tiny},
598enlargelimits=0.15,
599legend style={at={(0.5,-0.15)},
600anchor=north,legend columns=-1},
601ybar,
602bar width=7pt,
603]
604\addplot
605file {data/ipc1.dat};
606\addplot
607file {data/ipc2.dat};
608\addplot
609file {data/ipc3.dat};
610
611\legend{Bitstreams,NRGrep,Grep,Annot}
612\end{axis}
613\end{tikzpicture}
614\end{center}
615\caption{Instructions per Cycle}
616\end{figure}
617
618\begin{figure}
619\begin{center}
620\begin{tikzpicture}
621\begin{axis}[
622xtick=data,
623ylabel=Branch Misses per Byte,
624xticklabels={@,Date,Email,URIorEmail,xquote},
625tick label style={font=\tiny},
626enlargelimits=0.15,
627legend style={at={(0.5,-0.15)},
628anchor=north,legend columns=-1},
629ymax=0.03,
630ybar,
631bar width=7pt,
632]
633\addplot
634file {data/branch-misses1.dat};
635\addplot
636file {data/branch-misses2.dat};
637\addplot
638file {data/branch-misses3.dat};
639
640\legend{Bitstreams,NRGrep,Grep,Annot}
641\end{axis}
642\end{tikzpicture}
643\end{center}
644\caption{Branch Misses per Byte}
645\end{figure}
646
647
648
649\section{SIMD Scalability}\label{sec:AVX2}
650
651
652
653
654\begin{figure}
655\begin{center}
656\begin{tikzpicture}
657\begin{axis}[
658xtick=data,
659ylabel=Cycles per Byte,
660xticklabels={@,Date,Email,URIorEmail,xquote},
661tick label style={font=\tiny},
662enlargelimits=0.15,
663legend style={at={(0.5,-0.15)},
664anchor=north,legend columns=-1},
665ybar,
666bar width=7pt,
667]
668\addplot
669file {data/ssecycles.dat};
670\addplot
671file {data/avxcycles.dat};
672
673\legend{SSE2,AVX2,Annot}
674\end{axis}
675\end{tikzpicture}
676\end{center}
677\caption{Cycles per Byte}
678\end{figure}
679
680\begin{figure}
681\begin{center}
682\begin{tikzpicture}
683\begin{axis}[
684xtick=data,
685ylabel=Instructions per Byte,
686xticklabels={@,Date,Email,URIorEmail,xquote},
687tick label style={font=\tiny},
688enlargelimits=0.15,
689legend style={at={(0.5,-0.15)},
690anchor=north,legend columns=-1},
691ybar,
692bar width=7pt,
693]
694\addplot
695file {data/sseinstructions.dat};
696\addplot
697file {data/avxinstructions.dat};
698
699\legend{SSE2,AVX2,Annot}
700\end{axis}
701\end{tikzpicture}
702\end{center}
703\caption{Instructions per Byte}
704\end{figure}
705
706\begin{figure}
707\begin{center}
708\begin{tikzpicture}
709\begin{axis}[
710xtick=data,
711ylabel=Instructions per Cycle,
712xticklabels={@,Date,Email,URIorEmail,xquote},
713tick label style={font=\tiny},
714enlargelimits=0.15,
715legend style={at={(0.5,-0.15)},
716anchor=north,legend columns=-1},
717ybar,
718bar width=7pt,
719]
720\addplot
721file {data/sseipc.dat};
722\addplot
723file {data/avxipc.dat};
724
725
726\legend{SSE2,AVX2,Annot}
727\end{axis}
728\end{tikzpicture}
729\end{center}
730\caption{Instructions per Cycle}
731\end{figure}
732
733\begin{figure}
734\begin{center}
735\begin{tikzpicture}
736\begin{axis}[
737xtick=data,
738ylabel=Branch Misses per Byte,
739xticklabels={@,Date,Email,URIorEmail,xquote},
740tick label style={font=\tiny},
741enlargelimits=0.15,
742legend style={at={(0.5,-0.15)},
743anchor=north,legend columns=-1},
744ybar,
745bar width=7pt,
746]
747\addplot
748file {data/ssebranch-misses.dat};
749\addplot
750file {data/avxbranch-misses.dat};
751
752\legend{SSE2,AVX2,Annot}
753\end{axis}
754\end{tikzpicture}
755\end{center}
756\caption{Branch Misses per Byte}
757\end{figure}
758
759
760
761
762\subsection{AVX Stream Addition}
763 \begin{figure*}[tbh]
764\begin{center}
765\begin{verbatim}
766void add_ci_co(bitblock256_t x, bitblock256_t y, carry_t carry_in, carry_t & carry_out, bitblock256_t & sum) {
767  bitblock256_t all_ones = simd256<1>::constant<1>();
768  bitblock256_t gen = simd_and(x, y);
769  bitblock256_t prop = simd_xor(x, y);
770  bitblock256_t partial_sum = simd256<64>::add(x, y);
771  bitblock256_t carry = simd_or(gen, simd_andc(prop, partial_sum));
772  bitblock256_t bubble = simd256<64>::eq(partial_sum, all_ones);
773  uint64_t carry_mask = hsimd256<64>::signmask(carry) * 2 + convert(carry_in);
774  uint64_t bubble_mask = hsimd256<64>::signmask(bubble);
775  uint64_t carry_scan_thru_bubbles = (carry_mask + bubble_mask) &~ bubble_mask;
776  uint64_t increments = carry_scan_thru_bubbles | (carry_scan_thru_bubbles - carry_mask);
777  carry_out = convert(increments >> 4);
778  uint64_t spread = 0x0000200040008001 * increments & 0x0001000100010001;
779  sum = simd256<64>::add(partial_sum, _mm256_cvtepu16_epi64(avx_select_lo128(convert(spread))));
780}
781
782\end{verbatim}
783
784\end{center}
785\caption{AVX2 256-bit Addition}
786\label{fig:AVX2add}
787\end{figure*}
788
789\section{GPU Implementation}\label{sec:GPU}
790\begin{figure}
791\begin{center}
792\begin{tikzpicture}
793\begin{axis}[
794xtick=data,
795ylabel=Running Time (ms per byte),
796xticklabels={@,Date,Email,URIorEmail,xquote},
797tick label style={font=\tiny},
798enlargelimits=0.15,
799legend style={at={(0.5,-0.15)},
800anchor=north,legend columns=-1},
801ybar,
802bar width=7pt,
803]
804\addplot
805file {data/ssetime.dat};
806\addplot
807file {data/avxtime.dat};
808\addplot
809file {data/gputime.dat};
810
811\legend{SSE2,AVX2,GPU,Annot}
812\end{axis}
813\end{tikzpicture}
814\end{center}
815\caption{Running Time}
816\end{figure}
817
818
819
820
821\section{Miscellaneous}
822\subsection{Skipping}
823\input{re-Unicode}
824
825\input{conclusion}
826
827
828
829%\appendix
830%\section{Appendix Title}
831
832%This is the text of the appendix, if you need one.
833
834\acks
835
836This research was supported by grants from the Natural Sciences and Engineering Research Council of Canada and
837MITACS, Inc.
838
839% We recommend abbrvnat bibliography style.
840
841\bibliographystyle{abbrvnat}
842
843% The bibliography should be embedded for final submission.
844 
845\bibliography{reference}
846
847%\begin{thebibliography}{}
848%\softraggedright
849
850%\bibitem[Smith et~al.(2009)Smith, Jones]{smith02}
851%P. Q. Smith, and X. Y. Jones. ...reference text...
852%
853%\end{thebibliography}
854
855
856\end{document}
857
858
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