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10% Guide:        Refer to "Author's Guide to the ACM SIGPLAN Class,"
11%               sigplanconf-guide.pdf
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13% Author:       Paul C. Anagnostopoulos
14%               Windfall Software
15%               978 371-2316
16%               paul@windfall.com
17%
18% Created:      15 February 2005
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23\documentclass[preprint]{sigplanconf}
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31
32\usepackage{amsmath}
33\usepackage{pgfplots}
34
35\begin{document}
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37\special{papersize=8.5in,11in}
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40
41\conferenceinfo{PPoPP 2014}{February 15-19, 2014, Orlando, Florida, United States} 
42\copyrightyear{2013} 
43\copyrightdata{978-1-nnnn-nnnn-n/yy/mm} 
44\doi{nnnnnnn.nnnnnnn}
45
46% Uncomment one of the following two, if you are not going for the
47% traditional copyright transfer agreement.
48
49%\exclusivelicense                % ACM gets exclusive license to publish,
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51
52%\permissiontopublish             % ACM gets nonexclusive license to publish
53                                  % (paid open-access papers,
54                                  % short abstracts)
55
56\titlebanner{}        % These are ignored unless
57\preprintfooter{Bitwise Data Parallel Grep}   % 'preprint' option specified.
58
59\title{Bitwise Data Parallelism in Regular Expression Matching}
60%\subtitle{Subtitle Text, if any}
61
62\authorinfo{Anonymous Authors}{Institutions}{emails}
63%\authorinfo{Robert D. Cameron \and Kenneth S. Herdy \and Dan Lin \and Meng Lin \and Ben Hull \and Thomas S. Shermer \and Arrvindh Shriraman}
64%          {Simon Fraser University}
65%           {\{cameron,ksherdy,lindanl,linmengl,bhull,shermer,ashriram\}@cs.sfu.ca}
66
67\maketitle
68
69\begin{abstract}
70\input{abstract}
71\end{abstract}
72\category{Theory of computation}{Formal languages and automata theory}{Regular languages}
73\category{Computer systems organization}{Parallel architectures}{Single instruction, multiple data}
74
75% general terms are not compulsory anymore,
76% you may leave them out
77%\terms
78%term1, term2
79
80\keywords
81regular expression matching, grep, parallel bit stream technology
82
83\section{Introduction}
84
85The use of regular expressions to search texts for occurrences
86of string patterns has a long history and
87remains a pervasive technique throughout computing applications today.
88% {\em a brief history}
89The origins of regular expression matching date back to automata theory
90developed by Kleene in the 1950s \cite{kleene1951}.
91Thompson \cite{thompson1968} is credited with the first construction to convert regular expressions
92to nondeterministic finite automata (NFA).
93Following Thompson's approach, a regular expression of length $m$ is first converted
94to an NFA with $O(m)$ nodes. It is then possible to search a text of length $n$ using the
95NFA in worst case $O(mn)$ time. Often, a more efficient choice
96is to convert the NFA into a DFA. A DFA has only a single active state at any time
97in the matching process and
98hence it is possible to search a text at of length $n$ in $O(n)$ time.
99However, it is well known that the conversion of an NFA to an equivalent DFA may result
100in state explosion. That is, the number of resultant DFA states may increase exponentially.
101In \cite{Baeza-yates_anew} a new approach to text searching was proposed based on bit-parallelism \cite{baeza1992new}.
102This technique takes advantage of the intrinsic parallelism of bitwise operations
103within a computer word. Given a $w$-bit word, the Shift-Or algorithm \cite{Baeza-yates_anew} algorithm uses the
104bit-parallel approach to
105simulate an NFA in $O(nm/w)$ worst-case time.
106
107A disadvantage of the bit-parallel Shift-Or pattern matching approach
108in comparison to simple string matching algorithms is an inability to skip input characters.
109For example, the Boyer-Moore family of algorithms \cite{boyer1977fast} skip input characters
110to achieve sublinear times in the average case. Backward Dawg Matching
111(BDM) string matching algorithms \cite{crochemore1994text} based on suffix automata are able to skip characters.
112The Backward Nondeterministic Dawg Matching (BNDM) pattern matching algorithm \cite{wu1992fast} 
113combines the bit-parallel advantages of Shift-Or and with the character skipping advantages of the BDM algorithm.
114The nrgrep pattern matching tool is built over the BNDM algorithm,
115and hence the name nrgrep \cite{navarro2000}.
116
117There has been considerable interest in using parallelization techniques
118to improve the performance of regular expression matching on parallel hardware
119such as multi-core processors (CPUs), graphics processing units (GPUs),
120field-programmable gate arrays (FPGAs), and specialized architectures such as
121the Cell Broadband Engine (Cell BE). % FPGA results (synthesis of patterns into logic circuits) vs. memory based approaches (STTs in memory)
122%CPU
123Scarpazza and Braudaway \cite{scarpazza2008fast} demonstrated that
124text processing algorithms that exhibit irregular memory access patterns
125can be efficiently executed on multicore hardware.
126In related work, Pasetto et al. presented a flexible tool that
127performs small-ruleset regular expression matching at a rate of
1282.88 Gbps per chip on Intel Xeon E5472 hardware \cite{pasetto2010}.
129Naghmouchi et al. demonstrated that the Aho-Corasick (AC)
130string matching algorithm \cite{aho1975} is well suited for parallel
131implementation on multi-core CPUs, GPUs and the Cell BE \cite{scarpazza2011top, naghmouchi2010}.
132On each hardware, both thread-level parallelism (additional cores) and data-level parallelism
133(wide SIMD units) are leveraged for performance.
134Salapura et. al., advocated the use of vector-style processing for regular expressions
135in business analytics applications and leveraged the SIMD hardware available
136on multi-core processors to acheive a speedup of better than 1.8 over a
137range of data sizes of interest \cite{salapura2012accelerating}.
138%Cell
139In \cite{scarpazza2008}, Scarpazza and Russell presented a SIMD tokenizer
140that delivered 1.00–1.78 Gbps on a single
141Cell BE chip and extended this approach for emulation on the Intel Larrabee
142instruction set \cite{scarpazza2009larrabee}.
143On the Cell BE, Scarpazza \cite{scarpazza2009cell} described a pattern matching
144implementation that delivered a throughput of 40
145Gbps for a small dictionary of approximately 100 patterns, and a throughput of 3.3-3.4
146Gbps for a larger dictionary of thousands of patterns. Iorio and van Lunteren \cite{iorio2008} 
147presented a string matching implementation for automata that achieves
1484 Gbps on the Cell BE.
149% GPU
150In more recent work, Tumeo et al. \cite{tumeo2010efficient} presented a chunk-based
151implementation of the AC algorithm for
152accelerating string matching on GPUs. Lin et al., proposed
153the Parallel Failureless Aho-Corasick (PFAC)
154algorithm to accelerate pattern matching on GPU hardware and
155achieved 143 Gbps throughput, 14.74 times faster
156than the AC algorithm performed on a four core
157multi-core processor using OpenMP \cite{lin2013accelerating}.
158
159Whereas the existing approaches to parallelization have been
160based on adapting traditional sequential algorithms to emergent
161parallel architectures, we introduce both a new algorithmic
162approach and its implementation on SIMD and GPU architectures.
163This approach relies on a bitwise data parallel view of text
164streams as well as a surprising use of addition to match
165runs of characters in a single step.  The closest previous
166work is that underlying bit-parallel XML parsing using 128-bit SSE2 SIMD
167technology together with a parallel scanning primitive also
168based on addition \cite{cameron2011parallel}.   
169However, in contrast to the deterministic, longest-match
170scanning associated with the ScanThru primitive of that
171work, we introduce here a new primitive MatchStar
172that can be used in full generality for nondeterministic
173regular expression matching.   We also introduce a long-stream
174addition technique involving a further application of MatchStar
175that enables us to scale the technique to $n$-bit addition
176in $\lceil\log_{64}{n}\rceil$ steps.   We ultimately apply this technique,
177for example, to perform
178synchronized 4096-bit addition on GPU warps of 64 threads.
179
180There is also a strong keyword match between the bit-parallel
181data streams used in our approach and the bit-parallelism
182used for NFA state transitions in the classical algorithms of
183Wu and Manber \cite{wu1992agrep}, Baez-Yates and Gonnet \cite{baeza1992new}
184and Navarro and Raffinot \cite{navarro1998bit}.
185However those algorithms use bit-parallelism in a fundamentally
186different way: representing all possible current NFA states
187as a bit vector and performing parallel transitions to a new
188set of states using table lookups and bitwise logic.    Whereas
189our approach can match multiple characters per step, bit-parallel
190NFA algorithms proceed through the input one byte at a time.
191Nevertheless, the agrep \cite{wu1992agrep} and
192nrgrep \cite{navarro2000} programs implemented using these techniques remain
193among the strongest competitors in regular expression matching
194performance, so we include them in our comparative evaluation.
195
196The remainder of this paper is organized as follows.
197Section \ref{sec:grep} briefly describes regular expression
198notation and the grep problem.
199Section \ref{sec:bitwise} presents our basic algorithm and MatchStar
200using a model of arbitrary-length bit-parallel data streams.
201Section \ref{sec:blockwise} discusses the block-by-block
202implementation of our techniques including the long stream
203addition techniques for 256-bit addition with AVX2 and
2044096-bit additions with GPGPU SIMT.
205Section \ref{sec:analysis} 
206Section \ref{sec:SSE2} 
207Section \ref{sec:AVX2} 
208Section \ref{sec:GPU} 
209Section \ref{sec:Concl} concludes the paper with a discussion of areas for future work.
210
211\section{Regular Expression Notation and Grep}\label{sec:grep}
212
213We follow common Posix notation for regular expressions.
214A regular expression specifies a set of strings through
215a pattern notation.   Individual characters normally
216stand for themselves, unless they are one of the
217special characters \verb:*+?[{\(|^$.: that serve as metacharacters
218of the notation system.  Thus the regular expression \verb:cat:
219is a pattern for the set consisting of the single 3-character
220string ``\verb:cat:''.   The special characters must be escaped
221with a backslash to prevent interpretation as metacharacter, thus
222\verb:\$: represents the dollar-sign and \verb:\\\\: represent
223the string consisting of two backslash characters.
224Character class bracket expressions are pattern elements
225that allow any character in a given class to be used in a particular
226context.  For example, \verb:[@#%]: is a regular expression
227that stands for any of the three given symbols.  Contiguous
228ranges of characters may be specified using hyphens;
229for example \verb:[0-9]: for digits and \verb:[A-Za-z0-9_]:
230for any alphanumeric character or underscore.  If the
231caret character immediately follows the opening bracket,
232the class is negated, thus \verb:[^0-9]: stands for
233any character except a digit.  The period metacharacter
234\verb:.: stands for the class of all characters.
235
236Consecutive pattern elements stand for strings formed by
237concatenation, thus \verb:[cd][ao][tg]: stands for the
238set of 8 three-letter strings ``\verb:cat:'' through ``\verb:dog:''.
239The alternation operator \verb:|: allows a pattern to be
240defined to have to alternative forms, thus \verb:cat|dog:
241matches either ``\verb:cat:'' or ``\verb:dog:''.  Concatenation
242takes precedence over alternation, but parenthesis may be
243used to change this, thus \verb:(ab|cd)[0-9]: stands for any
244digit following one of the two prefixes  ``\verb:ab:'' or ``\verb:cd:''.
245
246Repetition operators may be appended to a pattern to specify
247a variable number of occurrences of that pattern. 
248The Kleene \verb:*: specifies zero-or-more occurrences
249matching the previous pattern, while \verb:+: specifies one-or
250more occurrences.  Thus \verb:[a-z][a-z]*: and \verb:[a-z]+:
251both specify the same set: strings of at least one lower-case
252letter.  The postfix operator \verb:?: specifies an optional
253component, i.e., zero-or-one occurrence of strings matching
254the element.  Specific bounds may be given within braces:
255\verb:(ab){3}: specifies the string ``\verb:ababab:'',
256\verb:[0-9A-Fa-f]{2,4}: specifies strings of two, three
257or four hexadecimal digits, and \verb:[A-Z]{4,}: specifies
258strings of at least 4 consecutive capital letters.
259
260The grep program searches a file for lines containing matches
261to a regular expression using any of the above notations.
262In addition, the pattern elements \verb:^: and \verb:$:
263may be used to match respectively the beginning or the
264end of a line.  In line-based tools such as grep, \verb:.:
265matches any character except newlines; matches cannot extend
266over lines.
267Normally, grep prints all matching
268lines to its output.  However, grep programs typically
269allow a command line flag such as \verb:-c: to specify
270that only a count of matching lines be produced; we use
271this option in our experimental evaluation to focus
272our comparisons on the performance of the underlying matching
273algorithms.
274
275\section{Matching with Bit-Parallel Data Streams}\label{sec:bitwise}
276
277Whereas the traditional approaches to regular expression matching
278using NFAs, DFAs or backtracking all rely on a byte-at-a-time
279processing model, the approach  we introduce in this paper is based
280on quite a different concept:  a data-parallel approach to simultaneous
281processing of data stream elements.  Indeed, our most abstract model
282is that of unbounded data parallelism: processing all elements of
283the input data stream simultaneously.   In essence, data streams are viewed
284as (very large) integers.   The fundamental operations are bitwise
285logic, stream shifting and long-stream addition.
286
287Depending on the available parallel processing resources, an actual
288implementation may divide an input stream into blocks  and process
289the blocks sequentially.   Within each block  all elements of the
290input stream are processed together, relying the availability of
291bitwise logic and addition scaled to the block size.   On commodity
292Intel and AMD processors with 128-bit SIMD capabilities (SSE2),
293we typically process input streams 128 bytes at a time.   In this
294case, we rely on the Parabix tool chain \cite{lin2012parabix}
295to handle the details of compilation to block-by-block processing.
296For our GPGPU implementation, we have developed a long-stream
297addition technique that allows us to perform 4096-bit additions
298using 64 threads working in lock-step SIMT fashion.  Using scripts
299to modify the output of the Parabix tools, we effectively divide
300the input into blocks of 4K bytes processed in a fully data-parallel
301manner.
302
303\begin{figure}[tbh]
304\begin{center}
305\begin{tabular}{cr}\\
306input data  & \verb`a4534q--b29z---az---a4q--bca22z--`\\
307$B_7$ & \verb`.................................`\\
308$B_6$ & \verb`1....1..1..1...11...1.1..111..1..`\\
309$B_5$ & \verb`111111111111111111111111111111111`\\
310$B_4$ & \verb`.11111...111....1....11.....111..`\\
311$B_3$ & \verb`......11..11111.1111...11.....111`\\
312$B_2$ & \verb`.11.1.11....111..111.1.11......11`\\
313$B_1$ & \verb`...1....11.1....1........11.111..`\\
314$B_0$ & \verb`1.11.111..1.1111.1111.111.11...11`\\
315\verb:[a]: & \verb`1..............1....1......1.....`\\
316\verb:[z]: & \verb`...........1....1.............1..`\\
317\verb:[0-9]: & \verb`.1111....11..........1......11...`
318\end{tabular}
319
320\end{center}
321\caption{Basis and Character Class Streams}
322\label{fig:streams}
323\end{figure}
324
325A key concept in this streaming approach is the derivation of bit streams
326that are parallel to the input data stream, i.e., in one-to-one
327correspondence with the data element positions of the input
328streams.   Typically, the input stream is a byte stream comprising
329the 8-bit character code units of a particular encoding such
330as extended ASCII, ISO-8859-1 or UTF-8.   However, the method may also
331easily be used with wider code units such as the 16-bit code units of
332UTF-16.   In the case of a byte stream, the first step is to transpose
333the byte stream into eight parallel bit streams, such that bit stream
334$i$ comprises the $i^\text{th}$ bit of each byte.   These streams form
335a set of basis bit streams from which many other parallel bit
336streams can be calculated, such as character class bit
337streams such that each bit $j$ of the stream specifies
338whether character $j$ of the input stream is in the class
339or not.  Figure \ref{fig:streams} shows an example of an
340input byte stream in ASCII, the eight basis bit streams of the
341transposed representation, and the character class bit streams
342\verb:[a]:,
343\verb:[z]:, and
344\verb:[0-9]:
345that may be computed from the basis bit streams using bitwise logic.
346Zero bits are marked with periods ({\tt .}) so that the one bits stand out.
347Transposition and character class construction are straightforward
348using the Parabix tool chain \cite{lin2012parabix}.
349
350\begin{figure}[tbh]
351\begin{center}
352\begin{tabular}{cr}\\
353input data  & \verb`a4534q--b29z---az---a4q--bca22z--`\\
354$M_1$ & \verb`.1..............1....1......1....`\\
355$M_2$ & \verb`.11111..........1....11.....111..`\\
356$M_3$ & \verb`.................1.............1.`
357\end{tabular}
358
359\end{center}
360\caption{Marker Streams in Matching {\tt a[0-9]*z}}
361\label{fig:streams2}
362\end{figure}
363
364\paragraph*{Marker Streams.}  Now consider how bit-parallel data
365streams can be used in regular expression matching.   Consider
366the problem of searching the input stream of Figure \ref{fig:streams}
367to finding occurrence of strings matching
368the regular expression \verb:a[0-9]*z:.
369The matching process involves the concept of {\em marker streams}, that
370is streams that mark the positions of current matches during the
371overall process.  In this case there are three marker streams computed
372during the match process, namely,
373$M_1$ representing match positions after an initial \verb:a:
374character has been found, $M_2$ representing positions
375reachable from positions marked by $M_1$ by further matching zero or
376more digits (\verb:[0-9]*:) and finally $M_3$ the stream
377marking positions after a final \verb:z: has been found.
378Without describing the details of how these streams are computed
379for the time being, Figure \ref{fig:streams2} shows what each
380of these streams should be for our example matching problem.
381Note our convention that a marker stream contains a 1 bit
382at the next character position to be matched, that is,
383immediately past the last position that was matched.
384
385
386\paragraph*{MatchStar.}
387MatchStar takes a marker bitstream and a character class bitstream as input.  It returns all positions that can be reached by advancing the marker bitstream zero or more times through the character class bitstream.
388
389\begin{figure}[tbh]
390\begin{center}
391\begin{tabular}{cr}\\
392input data  & \verb`a4534q--b29z---az---a4q--bca22z--`\\
393$M_1$ & \verb`.1..............1....1......1....`\\
394$D = \text{\tt [0-9]}$ & \verb`.1111....11..........1......11...`\\
395$T_0 = M_1 \wedge D$ & \verb`.1...................1......1....`\\
396$T_1 = T_0 + D$ & \verb`.....1...11...........1.......1..`\\
397$T_2 = T_1 \oplus D$ & \verb`.11111...............11.....111..`\\
398$M_2 = T_2 \, | \, M_1$ & \verb`.11111..........1....11.....111..`
399\end{tabular}
400
401\end{center}
402\caption{$M_2 = \text{MatchStar}(M_1, D)$}
403\label{fig:matchstar}
404\end{figure}
405
406
407Figure \ref{fig:matchstar} illustrates the MatchStar method.  The second and third rows are the input bitstreams: the initial marker position bitstream and the character class bitstream derived from the source data. 
408
409It is important to note that our bitstreams are shown in natural left-to-right order reflecting the
410conventional presentation of our character data input.   However, this reverses the normal
411order of presentation when considering bitstreams as numeric values.  The key point here is
412that when we perform bitstream addition, we will show bit movement from left-to-right.
413That $\verb:111.: + \verb:1...: = \verb:...1:$
414
415In the first operation ($T_0$), marker positions that cannot be advanced are temporarily removed from consideration by masking off marker positions that aren't character class positions using bitwise logic.  Next, the temporary marker bitstream is added to the character class bitstream. 
416The addition produces 1s in three types of positions.  There will be a 1 immediately following a block of character class positions that spanned one or more marker positions, at any character class positions that weren't affected by the addition (and are not part of the desired output), and at any marker position that wasn't the first in its block of character class positions.  Any character class positions that have a 0 in $T_1$ were affected by the addition and are part of the desired output.  These positions are obtained and the undesired 1 bits are removed by XORing with the character class stream. $T_2$ is now only missing marker positions that were removed in the first step as well as marker positions that were 1s in $T_1$.  The
417output marker stream is obtained by ORing $T_2$ with the initial marker stream.
418
419In general, given a marker stream $M$ and a character class stream $C$,
420the operation of MatchStar is defined by the following equation. 
421\[\text{MatchStar}(M, C) = (((M \wedge C) + C)  \oplus C) | M\]
422Given a set of initial marker positions, the result stream marks
423all possible positions that can be reached by 0 or more occurrences
424of characters in class $C$ from each position in $M$
425
426
427
428
429\section{Block-at-a-Time Processing}\label{sec:blockwise}
430
431The unbounded stream model of the previous section must of course
432be translated an implementation that proceeds block-at-a-time for
433realistic application.  In this, we primarily rely on the Pablo
434compiler of the Parabix toolchain \cite{lin2012parabix}.  Given input
435statements expressed as arbitrary-length bitstream equations, Pablo
436produces block-at-a-time C++ code that initializes and maintains all the necessary
437carry bits for each of the additions and shifts involved in the
438bitstream calculations.   
439
440In the present work, our principal contribution to the block-at-a-time
441model is the technique of long-stream addition described below.
442Otherwise, we were able to use Pablo directly in compiling our
443SSE2 and AVX2 implementations.   Our GPU implementation required
444some scripting to modify the output of the Pablo compiler for our
445purpose.
446
447\paragraph*{Long-Stream Addition.}  The maximum word size for
448addition on commodity processors is typically 64 bits.  In order
449to implement long-stream addition for block sizes of 256 or larger,
450a method for propagating carries through the individual stages of
45164-bit addition is required.  However, the normal technique of
452sequential addition using add-with-carry instructions, for example,
453is far from ideal.
454
455We have developed a technique using SIMD or SIMT methods for constant-time
456long-stream addition up to 4096 bits.   
457We assume the availability of the following SIMD/SIMT operations
458operating on vectors of $f$ 64-bit fields.
459\begin{itemize}
460\item \verb#simd<64>::add(X, Y)#: vertical SIMD addition of corresponding 64-bit fields
461in two vectors to produce a result vector of $f$ 64-bit fields.
462\item  \verb#simd<64>::eq(X, -1)# :  comparison of the 64-bit fields
463of \verb:x: each with the constant value -1 (all bits 1), producing
464an $f$-bit mask value,
465\item  \verb#hsimd<64>::mask(X)# : gathering the high bit of each 64-bit
466field into a single compressed $f$-bit mask value, and
467\item normal bitwise logic operations on $f$-bit masks, and
468\item  \verb#simd<64>::spread(x)# : distributing the bits of
469an $f$ bit mask, one bit each to the $f$ 64-bit fields of a vector.
470\end{itemize}
471
472Given these operations, our method for long stream addition of
473two $f \times 64$ bit values \verb:X: and \verb:Y: is the following.
474\begin{enumerate}
475\item Form the vector of 64-bit sums of \verb:x: and \verb:y:.
476\[\text{\tt R} = \text{\tt simd<64>::add(X, Y)} \]
477
478\item Extract the $f$-bit masks of \verb:X:, \verb:Y: and \verb:R:.
479\[\text{\tt x} = \text{\tt hsimd<64>::mask(X)} \]
480\[\text{\tt y} = \text{\tt hsimd<64>::mask(Y)} \]
481\[\text{\tt r} = \text{\tt hsimd<64>::mask(R)} \]
482
483\item Compute an $f$-bit mask of carries generated for each of the
48464-bit additions of \verb:X: and \verb:Y:.
485\[\text{\tt c} = (\text{\tt x} \wedge \text{\tt y}) \vee ((\text{\tt x} \vee \text{\tt y}) \wedge \neg \text{\tt r})\]
486
487\item Compute an $f$-bit mask of all fields of {\tt R} that will overflow with
488an incoming carry bit.  This is the {\em bubble mask}.
489\[\text{\tt b} = \text{\tt simd<64>::eq(R, -1)}\]
490
491\item Determine an $f$-bit mask identifying the fields of {\tt R} that need to be
492incremented to produce the final sum.  Here we find a new application of
493MatchStar!
494\[\text{\tt i} = \text{\tt MatchStar(c*2, b)}\]
495
496This is the key step.  The mask {\tt c} of outgoing carries must be
497shifted one position ({\tt c*2}) so that each outgoing carry bit becomes associated
498with the next digit.  At the incoming position, the carry will
499increment the 64-bit digit.   However, if this digit is all ones (as
500signalled by the corresponding bit of bubble mask {\tt b}, then the addition
501will generate another carry.  In fact, if there is a sequence of
502digits that are all ones, then the carry must bubble through
503each of them.   This is just MatchStar!
504
505\item Compute the final result {\tt Z}.
506\[\text{\tt Z} = \text{\tt simd<64>::add(R, simd<64>::spread(i))}\]
507
508\end{enumerate}
509\begin{figure}
510\begin{center}
511\begin{tabular}{c||r|r|r|r|r|r|r|r||}\cline{2-9}
512{\tt X} & {\tt 19} & {\tt 31} & {\tt BA} & {\tt 4C} & {\tt 3D} & {\tt 45} & {\tt 21} & {\tt F1} \\ \cline{2-9}
513{\tt Y} & {\tt 22} & {\tt 12} & {\tt 45} & {\tt B3} & {\tt E2} & {\tt 16} & {\tt 17} & {\tt 36} \\ \cline{2-9}
514{\tt R} & {\tt 3B} & {\tt 43} & {\tt FF} & {\tt FF} & {\tt 1F} & {\tt 5B} & {\tt 38} & {\tt 27} \\ \cline{2-9}
515{\tt x} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} \\ \cline{2-9}
516{\tt y} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
517{\tt r} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
518{\tt c} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} \\ \cline{2-9}
519{\tt c*2} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} \\ \cline{2-9}
520{\tt b} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 0} & {\tt 0} \\ \cline{2-9}
521{\tt i} & {\tt 0} & {\tt 1} & {\tt 1} & {\tt 1} & {\tt 0} & {\tt 0} & {\tt 1} & {\tt 0} \\ \cline{2-9}
522{\tt Z} & {\tt 3B} & {\tt 44} & {\tt 0} & {\tt 0} & {\tt 1F} & {\tt 5B} & {\tt 39} & {\tt 27} \\ \cline{2-9}
523\end{tabular}
524\end{center}
525\caption{Long Stream Addition}\label{fig:longadd}
526\end{figure}
527
528Figure \ref{fig:longadd} illustrates the process.  In the figure,
529we illustrate the process with 8-bit fields rather than 64-bit fields
530and show all field values in hexadecimal notation.  Note that
531two of the individual 8-bit additions produce carries, while two
532others produce {\tt FF} values that generate bubble bits.  The
533net result is that four of the original 8-bit sums must be
534incremented to produce the long stream result.
535
536A slight extension to the process produces a long-stream full adder
537that can be used in chained addition.  In this case, the
538adder must take an additional carry-in bit
539{\tt p} and produce a carry-out bit {\tt q}.
540This may be accomplished by incorporating {\tt p}
541in calculating the increment mask in the low bit position,
542and then extracting the carry-out {\tt q} from the high bit position.
543\[\text{\tt i} = \text{\tt MatchStar(c*2+p, b)}\]
544\[\text{\tt q} = \text{\tt i >> f}\]
545
546As described subsequently, we use a two-level long-stream addition technique
547in both our AVX2 and GPU implementations.  In principle, one can extend
548the technique to additional levels.  Using 64-bit adders throughout,
549$\lceil\log_{64}{n}\rceil$ steps are needed for $n$-bit addition.
550A three-level scheme could coordinate
55164 groups each performing 4096-bit long additions in a two-level structure.
552However, whether there are reasonable architectures that can support fine-grained
553SIMT style coordinate at this level is an open question.
554
555Using the methods outlined, it is quite conceivable that instruction
556set extensions to support long-stream addition could be added for
557future SIMD and GPU processors.   Given the fundamental nature
558of addition as a primitive and its novel application to regular
559expression matching as shown herein, it seems reasonable to expect
560such instructions to become available.
561\raggedbottom
562\section{Analytical Comparison with DFA and NFA Implementations}\label{sec:analysis}
563
564\begin{enumerate}
565\item Operations
566\item Memory behaviour per input byte: note tables of DFA/NFA.
567
568Bille and Throup \em{Faster regular expression matching}\cite{bille2009faster}
569
570\end{enumerate}
571
572
573
574\section{Commodity SIMD Implementation and Experimental Evaluation}\label{sec:SSE2}
575
576
577\subsection{Implementation Notes}
578\subsection{Evaluation Methodology}
579\subsection{Comparison}
580\begin{figure}
581\begin{center}
582\begin{tikzpicture}
583\begin{axis}[
584xtick=data,
585ylabel=Cycles per Byte,
586xticklabels={@,Date,Email,URIorEmail,xquote},
587tick label style={font=\tiny},
588enlargelimits=0.15,
589legend style={at={(0.5,-0.15)},
590anchor=north,legend columns=-1},
591ymax=8,
592ybar,
593bar width=7pt,
594]
595\addplot
596file {data/cycles1.dat};
597\addplot
598file {data/cycles2.dat};
599\addplot
600file {data/cycles3.dat};
601 
602\legend{Bitstreams,NRGrep,Grep,Annot}
603\end{axis}
604\end{tikzpicture}
605\end{center}
606\caption{Cycles per Byte}
607\end{figure}
608 
609\begin{figure}
610\begin{center}
611\begin{tikzpicture}
612\begin{axis}[
613xtick=data,
614ylabel=Instructions per Byte,
615xticklabels={@,Date,Email,URIorEmail,xquote},
616tick label style={font=\tiny},
617enlargelimits=0.15,
618legend style={at={(0.5,-0.15)},
619anchor=north,legend columns=-1},
620ymax=16,
621ybar,
622bar width=7pt,
623]
624\addplot
625file {data/instructions1.dat};
626\addplot
627file {data/instructions2.dat};
628\addplot
629file {data/instructions3.dat};
630 
631\legend{Bitstreams,NRGrep,Grep,Annot}
632\end{axis}
633\end{tikzpicture}
634\end{center}
635\caption{Instructions per Byte}
636\end{figure}
637
638\begin{figure}
639\begin{center}
640\begin{tikzpicture}
641\begin{axis}[
642xtick=data,
643ylabel=Instructions per Cycle,
644xticklabels={@,Date,Email,URIorEmail,xquote},
645tick label style={font=\tiny},
646enlargelimits=0.15,
647legend style={at={(0.5,-0.15)},
648anchor=north,legend columns=-1},
649ybar,
650bar width=7pt,
651]
652\addplot
653file {data/ipc1.dat};
654\addplot
655file {data/ipc2.dat};
656\addplot
657file {data/ipc3.dat};
658
659\legend{Bitstreams,NRGrep,Grep,Annot}
660\end{axis}
661\end{tikzpicture}
662\end{center}
663\caption{Instructions per Cycle}
664\end{figure}
665
666\begin{figure}
667\begin{center}
668\begin{tikzpicture}
669\begin{axis}[
670xtick=data,
671ylabel=Branch Misses per Byte,
672xticklabels={@,Date,Email,URIorEmail,xquote},
673tick label style={font=\tiny},
674enlargelimits=0.15,
675legend style={at={(0.5,-0.15)},
676anchor=north,legend columns=-1},
677ymax=0.03,
678ybar,
679bar width=7pt,
680]
681\addplot
682file {data/branch-misses1.dat};
683\addplot
684file {data/branch-misses2.dat};
685\addplot
686file {data/branch-misses3.dat};
687
688\legend{Bitstreams,NRGrep,Grep,Annot}
689\end{axis}
690\end{tikzpicture}
691\end{center}
692\caption{Branch Misses per Byte}
693\end{figure}
694
695
696
697\section{SIMD Scalability}\label{sec:AVX2}
698
699
700
701
702\begin{figure}
703\begin{center}
704\begin{tikzpicture}
705\begin{axis}[
706xtick=data,
707ylabel=Cycles per Byte,
708xticklabels={@,Date,Email,URIorEmail,xquote},
709tick label style={font=\tiny},
710enlargelimits=0.15,
711legend style={at={(0.5,-0.15)},
712anchor=north,legend columns=-1},
713ybar,
714bar width=7pt,
715]
716\addplot
717file {data/ssecycles.dat};
718\addplot
719file {data/avxcycles.dat};
720
721\legend{SSE2,AVX2,Annot}
722\end{axis}
723\end{tikzpicture}
724\end{center}
725\caption{Cycles per Byte}
726\end{figure}
727
728\begin{figure}
729\begin{center}
730\begin{tikzpicture}
731\begin{axis}[
732xtick=data,
733ylabel=Instructions per Byte,
734xticklabels={@,Date,Email,URIorEmail,xquote},
735tick label style={font=\tiny},
736enlargelimits=0.15,
737legend style={at={(0.5,-0.15)},
738anchor=north,legend columns=-1},
739ybar,
740bar width=7pt,
741]
742\addplot
743file {data/sseinstructions.dat};
744\addplot
745file {data/avxinstructions.dat};
746
747\legend{SSE2,AVX2,Annot}
748\end{axis}
749\end{tikzpicture}
750\end{center}
751\caption{Instructions per Byte}
752\end{figure}
753
754\begin{figure}
755\begin{center}
756\begin{tikzpicture}
757\begin{axis}[
758xtick=data,
759ylabel=Instructions per Cycle,
760xticklabels={@,Date,Email,URIorEmail,xquote},
761tick label style={font=\tiny},
762enlargelimits=0.15,
763legend style={at={(0.5,-0.15)},
764anchor=north,legend columns=-1},
765ybar,
766bar width=7pt,
767]
768\addplot
769file {data/sseipc.dat};
770\addplot
771file {data/avxipc.dat};
772
773
774\legend{SSE2,AVX2,Annot}
775\end{axis}
776\end{tikzpicture}
777\end{center}
778\caption{Instructions per Cycle}
779\end{figure}
780
781\begin{figure}
782\begin{center}
783\begin{tikzpicture}
784\begin{axis}[
785xtick=data,
786ylabel=Branch Misses per Byte,
787xticklabels={@,Date,Email,URIorEmail,xquote},
788tick label style={font=\tiny},
789enlargelimits=0.15,
790legend style={at={(0.5,-0.15)},
791anchor=north,legend columns=-1},
792ybar,
793bar width=7pt,
794]
795\addplot
796file {data/ssebranch-misses.dat};
797\addplot
798file {data/avxbranch-misses.dat};
799
800\legend{SSE2,AVX2,Annot}
801\end{axis}
802\end{tikzpicture}
803\end{center}
804\caption{Branch Misses per Byte}
805\end{figure}
806
807
808
809
810\subsection{AVX Stream Addition}
811 \begin{figure*}[tbh]
812\begin{center}
813\begin{verbatim}
814void add_ci_co(bitblock256_t x, bitblock256_t y, carry_t carry_in, carry_t & carry_out, bitblock256_t & sum) {
815  bitblock256_t all_ones = simd256<1>::constant<1>();
816  bitblock256_t gen = simd_and(x, y);
817  bitblock256_t prop = simd_xor(x, y);
818  bitblock256_t partial_sum = simd256<64>::add(x, y);
819  bitblock256_t carry = simd_or(gen, simd_andc(prop, partial_sum));
820  bitblock256_t bubble = simd256<64>::eq(partial_sum, all_ones);
821  uint64_t carry_mask = hsimd256<64>::signmask(carry) * 2 + convert(carry_in);
822  uint64_t bubble_mask = hsimd256<64>::signmask(bubble);
823  uint64_t carry_scan_thru_bubbles = (carry_mask + bubble_mask) &~ bubble_mask;
824  uint64_t increments = carry_scan_thru_bubbles | (carry_scan_thru_bubbles - carry_mask);
825  carry_out = convert(increments >> 4);
826  uint64_t spread = 0x0000200040008001 * increments & 0x0001000100010001;
827  sum = simd256<64>::add(partial_sum, _mm256_cvtepu16_epi64(avx_select_lo128(convert(spread))));
828}
829
830\end{verbatim}
831
832\end{center}
833\caption{AVX2 256-bit Addition}
834\label{fig:AVX2add}
835\end{figure*}
836
837\section{GPU Implementation}\label{sec:GPU}
838\begin{figure}
839\begin{center}
840\begin{tikzpicture}
841\begin{axis}[
842xtick=data,
843ylabel=Running Time (ms per byte),
844xticklabels={@,Date,Email,URIorEmail,xquote},
845tick label style={font=\tiny},
846enlargelimits=0.15,
847legend style={at={(0.5,-0.15)},
848anchor=north,legend columns=-1},
849ybar,
850bar width=7pt,
851]
852\addplot
853file {data/ssetime.dat};
854\addplot
855file {data/avxtime.dat};
856\addplot
857file {data/gputime.dat};
858
859\legend{SSE2,AVX2,GPU,Annot}
860\end{axis}
861\end{tikzpicture}
862\end{center}
863\caption{Running Time}
864\end{figure}
865
866
867
868
869\section{Miscellaneous}
870\subsection{Skipping}
871\input{re-Unicode}
872
873\input{conclusion}
874
875
876
877%\appendix
878%\section{Appendix Title}
879
880%This is the text of the appendix, if you need one.
881
882\acks
883
884This research was supported by grants from the Natural Sciences and Engineering Research Council of Canada and
885MITACS, Inc.
886
887% We recommend abbrvnat bibliography style.
888
889\bibliographystyle{abbrvnat}
890
891% The bibliography should be embedded for final submission.
892 
893\bibliography{reference}
894
895%\begin{thebibliography}{}
896%\softraggedright
897
898%\bibitem[Smith et~al.(2009)Smith, Jones]{smith02}
899%P. Q. Smith, and X. Y. Jones. ...reference text...
900%
901%\end{thebibliography}
902
903
904\end{document}
905
906
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