source: icGREP/icgrep-devel/llvm-3.5.0.src/lib/Target/R600/R600Instructions.td @ 4574

Last change on this file since 4574 was 4574, checked in by cameron, 4 years ago

Updating to LLVM 3.6

File size: 52.8 KB
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1//===-- R600Instructions.td - R600 Instruction defs  -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// TableGen definitions for instructions which are available on R600 family
11// GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15include "R600Intrinsics.td"
16include "R600InstrFormats.td"
17
18class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
19    InstR600 <outs, ins, asm, pattern, NullALU> {
20
21  let Namespace = "AMDGPU";
22}
23
24def MEMxi : Operand<iPTR> {
25  let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
26  let PrintMethod = "printMemOperand";
27}
28
29def MEMrr : Operand<iPTR> {
30  let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index);
31}
32
33// Operands for non-registers
34
35class InstFlag<string PM = "printOperand", int Default = 0>
36    : OperandWithDefaultOps <i32, (ops (i32 Default))> {
37  let PrintMethod = PM;
38}
39
40// src_sel for ALU src operands, see also ALU_CONST, ALU_PARAM registers
41def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))> {
42  let PrintMethod = "printSel";
43}
44def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
45  let PrintMethod = "printBankSwizzle";
46}
47
48def LITERAL : InstFlag<"printLiteral">;
49
50def WRITE : InstFlag <"printWrite", 1>;
51def OMOD : InstFlag <"printOMOD">;
52def REL : InstFlag <"printRel">;
53def CLAMP : InstFlag <"printClamp">;
54def NEG : InstFlag <"printNeg">;
55def ABS : InstFlag <"printAbs">;
56def UEM : InstFlag <"printUpdateExecMask">;
57def UP : InstFlag <"printUpdatePred">;
58
59// XXX: The r600g finalizer in Mesa expects last to be one in most cases.
60// Once we start using the packetizer in this backend we should have this
61// default to 0.
62def LAST : InstFlag<"printLast", 1>;
63def RSel : Operand<i32> {
64  let PrintMethod = "printRSel";
65}
66def CT: Operand<i32> {
67  let PrintMethod = "printCT";
68}
69
70def FRAMEri : Operand<iPTR> {
71  let MIOperandInfo = (ops R600_Reg32:$ptr, i32imm:$index);
72}
73
74def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
75def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
76def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
77def ADDRGA_CONST_OFFSET : ComplexPattern<i32, 1, "SelectGlobalValueConstantOffset", [], []>;
78def ADDRGA_VAR_OFFSET : ComplexPattern<i32, 2, "SelectGlobalValueVariableOffset", [], []>;
79
80
81def R600_Pred : PredicateOperand<i32, (ops R600_Predicate),
82                                     (ops PRED_SEL_OFF)>;
83
84
85let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
86
87// Class for instructions with only one source register.
88// If you add new ins to this instruction, make sure they are listed before
89// $literal, because the backend currently assumes that the last operand is
90// a literal.  Also be sure to update the enum R600Op1OperandIndex::ROI in
91// R600Defines.h, R600InstrInfo::buildDefaultInstruction(),
92// and R600InstrInfo::getOperandIdx().
93class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
94                InstrItinClass itin = AnyALU> :
95    InstR600 <(outs R600_Reg32:$dst),
96              (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
97                   R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
98                   LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
99                   BANK_SWIZZLE:$bank_swizzle),
100              !strconcat("  ", opName,
101                   "$clamp $last $dst$write$dst_rel$omod, "
102                   "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
103                   "$pred_sel $bank_swizzle"),
104              pattern,
105              itin>,
106    R600ALU_Word0,
107    R600ALU_Word1_OP2 <inst> {
108
109  let src1 = 0;
110  let src1_rel = 0;
111  let src1_neg = 0;
112  let src1_abs = 0;
113  let update_exec_mask = 0;
114  let update_pred = 0;
115  let HasNativeOperands = 1;
116  let Op1 = 1;
117  let ALUInst = 1;
118  let DisableEncoding = "$literal";
119  let UseNamedOperandTable = 1;
120
121  let Inst{31-0}  = Word0;
122  let Inst{63-32} = Word1;
123}
124
125class R600_1OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
126                    InstrItinClass itin = AnyALU> :
127    R600_1OP <inst, opName,
128              [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
129>;
130
131// If you add or change the operands for R600_2OP instructions, you must
132// also update the R600Op2OperandIndex::ROI enum in R600Defines.h,
133// R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
134class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
135                InstrItinClass itin = AnyALU> :
136  InstR600 <(outs R600_Reg32:$dst),
137          (ins UEM:$update_exec_mask, UP:$update_pred, WRITE:$write,
138               OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
139               R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
140               R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
141               LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
142               BANK_SWIZZLE:$bank_swizzle),
143          !strconcat("  ", opName,
144                "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
145                "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
146                "$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
147                "$pred_sel $bank_swizzle"),
148          pattern,
149          itin>,
150    R600ALU_Word0,
151    R600ALU_Word1_OP2 <inst> {
152
153  let HasNativeOperands = 1;
154  let Op2 = 1;
155  let ALUInst = 1;
156  let DisableEncoding = "$literal";
157  let UseNamedOperandTable = 1;
158
159  let Inst{31-0}  = Word0;
160  let Inst{63-32} = Word1;
161}
162
163class R600_2OP_Helper <bits<11> inst, string opName, SDPatternOperator node,
164                       InstrItinClass itin = AnyALU> :
165    R600_2OP <inst, opName,
166              [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
167                                           R600_Reg32:$src1))], itin
168>;
169
170// If you add our change the operands for R600_3OP instructions, you must
171// also update the R600Op3OperandIndex::ROI enum in R600Defines.h,
172// R600InstrInfo::buildDefaultInstruction(), and
173// R600InstrInfo::getOperandIdx().
174class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
175                InstrItinClass itin = AnyALU> :
176  InstR600 <(outs R600_Reg32:$dst),
177          (ins REL:$dst_rel, CLAMP:$clamp,
178               R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
179               R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
180               R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
181               LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal,
182               BANK_SWIZZLE:$bank_swizzle),
183          !strconcat("  ", opName, "$clamp $last $dst$dst_rel, "
184                             "$src0_neg$src0$src0_rel, "
185                             "$src1_neg$src1$src1_rel, "
186                             "$src2_neg$src2$src2_rel, "
187                             "$pred_sel"
188                             "$bank_swizzle"),
189          pattern,
190          itin>,
191    R600ALU_Word0,
192    R600ALU_Word1_OP3<inst>{
193
194  let HasNativeOperands = 1;
195  let DisableEncoding = "$literal";
196  let Op3 = 1;
197  let UseNamedOperandTable = 1;
198  let ALUInst = 1;
199
200  let Inst{31-0}  = Word0;
201  let Inst{63-32} = Word1;
202}
203
204class R600_REDUCTION <bits<11> inst, dag ins, string asm, list<dag> pattern,
205                      InstrItinClass itin = VecALU> :
206  InstR600 <(outs R600_Reg32:$dst),
207          ins,
208          asm,
209          pattern,
210          itin>;
211
212
213
214} // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
215
216def TEX_SHADOW : PatLeaf<
217  (imm),
218  [{uint32_t TType = (uint32_t)N->getZExtValue();
219    return (TType >= 6 && TType <= 8) || TType == 13;
220  }]
221>;
222
223def TEX_RECT : PatLeaf<
224  (imm),
225  [{uint32_t TType = (uint32_t)N->getZExtValue();
226    return TType == 5;
227  }]
228>;
229
230def TEX_ARRAY : PatLeaf<
231  (imm),
232  [{uint32_t TType = (uint32_t)N->getZExtValue();
233    return TType == 9 || TType == 10 || TType == 16;
234  }]
235>;
236
237def TEX_SHADOW_ARRAY : PatLeaf<
238  (imm),
239  [{uint32_t TType = (uint32_t)N->getZExtValue();
240    return TType == 11 || TType == 12 || TType == 17;
241  }]
242>;
243
244def TEX_MSAA : PatLeaf<
245  (imm),
246  [{uint32_t TType = (uint32_t)N->getZExtValue();
247    return TType == 14;
248  }]
249>;
250
251def TEX_ARRAY_MSAA : PatLeaf<
252  (imm),
253  [{uint32_t TType = (uint32_t)N->getZExtValue();
254    return TType == 15;
255  }]
256>;
257
258class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
259                 dag outs, dag ins, string asm, list<dag> pattern> :
260    InstR600ISA <outs, ins, asm, pattern>,
261    CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF  {
262
263  let rat_id = ratid;
264  let rat_inst = ratinst;
265  let rim         = 0;
266  // XXX: Have a separate instruction for non-indexed writes.
267  let type        = 1;
268  let rw_rel      = 0;
269  let elem_size   = 0;
270
271  let array_size  = 0;
272  let comp_mask   = mask;
273  let burst_count = 0;
274  let vpm         = 0;
275  let cf_inst = cfinst;
276  let mark        = 0;
277  let barrier     = 1;
278
279  let Inst{31-0} = Word0;
280  let Inst{63-32} = Word1;
281  let IsExport = 1;
282
283}
284
285class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
286    : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>,
287      VTX_WORD1_GPR {
288
289  // Static fields
290  let DST_REL = 0;
291  // The docs say that if this bit is set, then DATA_FORMAT, NUM_FORMAT_ALL,
292  // FORMAT_COMP_ALL, SRF_MODE_ALL, and ENDIAN_SWAP fields will be ignored,
293  // however, based on my testing if USE_CONST_FIELDS is set, then all
294  // these fields need to be set to 0.
295  let USE_CONST_FIELDS = 0;
296  let NUM_FORMAT_ALL = 1;
297  let FORMAT_COMP_ALL = 0;
298  let SRF_MODE_ALL = 0;
299
300  let Inst{63-32} = Word1;
301  // LLVM can only encode 64-bit instructions, so these fields are manually
302  // encoded in R600CodeEmitter
303  //
304  // bits<16> OFFSET;
305  // bits<2>  ENDIAN_SWAP = 0;
306  // bits<1>  CONST_BUF_NO_STRIDE = 0;
307  // bits<1>  MEGA_FETCH = 0;
308  // bits<1>  ALT_CONST = 0;
309  // bits<2>  BUFFER_INDEX_MODE = 0;
310
311  // VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
312  // is done in R600CodeEmitter
313  //
314  // Inst{79-64} = OFFSET;
315  // Inst{81-80} = ENDIAN_SWAP;
316  // Inst{82}    = CONST_BUF_NO_STRIDE;
317  // Inst{83}    = MEGA_FETCH;
318  // Inst{84}    = ALT_CONST;
319  // Inst{86-85} = BUFFER_INDEX_MODE;
320  // Inst{95-86} = 0; Reserved
321
322  // VTX_WORD3 (Padding)
323  //
324  // Inst{127-96} = 0;
325
326  let VTXInst = 1;
327}
328
329class LoadParamFrag <PatFrag load_type> : PatFrag <
330  (ops node:$ptr), (load_type node:$ptr),
331  [{ return isConstantLoad(dyn_cast<LoadSDNode>(N), 0); }]
332>;
333
334def load_param : LoadParamFrag<load>;
335def load_param_exti8 : LoadParamFrag<az_extloadi8>;
336def load_param_exti16 : LoadParamFrag<az_extloadi16>;
337
338def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">;
339
340def isR600toCayman : Predicate<
341                     "Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
342
343//===----------------------------------------------------------------------===//
344// R600 SDNodes
345//===----------------------------------------------------------------------===//
346
347def INTERP_PAIR_XY :  AMDGPUShaderInst <
348  (outs R600_TReg32_X:$dst0, R600_TReg32_Y:$dst1),
349  (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
350  "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
351  []>;
352
353def INTERP_PAIR_ZW :  AMDGPUShaderInst <
354  (outs R600_TReg32_Z:$dst0, R600_TReg32_W:$dst1),
355  (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
356  "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
357  []>;
358
359def CONST_ADDRESS: SDNode<"AMDGPUISD::CONST_ADDRESS",
360  SDTypeProfile<1, -1, [SDTCisInt<0>, SDTCisPtrTy<1>]>,
361  [SDNPVariadic]
362>;
363
364def DOT4 : SDNode<"AMDGPUISD::DOT4",
365  SDTypeProfile<1, 8, [SDTCisFP<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32>,
366      SDTCisVT<3, f32>, SDTCisVT<4, f32>, SDTCisVT<5, f32>,
367      SDTCisVT<6, f32>, SDTCisVT<7, f32>, SDTCisVT<8, f32>]>,
368  []
369>;
370
371def COS_HW : SDNode<"AMDGPUISD::COS_HW",
372  SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
373>;
374
375def SIN_HW : SDNode<"AMDGPUISD::SIN_HW",
376  SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>
377>;
378
379def TEXTURE_FETCH_Type : SDTypeProfile<1, 19, [SDTCisFP<0>]>;
380
381def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>;
382
383multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
384def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR,
385          (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw),
386          (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz),
387          (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z),
388          (i32 imm:$DST_SEL_W),
389          (i32 imm:$RESOURCE_ID), (i32 imm:$SAMPLER_ID),
390          (i32 imm:$COORD_TYPE_X), (i32 imm:$COORD_TYPE_Y), (i32 imm:$COORD_TYPE_Z),
391          (i32 imm:$COORD_TYPE_W)),
392          (inst R600_Reg128:$SRC_GPR,
393          imm:$srcx, imm:$srcy, imm:$srcz, imm:$srcw,
394          imm:$offsetx, imm:$offsety, imm:$offsetz,
395          imm:$DST_SEL_X, imm:$DST_SEL_Y, imm:$DST_SEL_Z,
396          imm:$DST_SEL_W,
397          imm:$RESOURCE_ID, imm:$SAMPLER_ID,
398          imm:$COORD_TYPE_X, imm:$COORD_TYPE_Y, imm:$COORD_TYPE_Z,
399          imm:$COORD_TYPE_W)>;
400}
401
402//===----------------------------------------------------------------------===//
403// Interpolation Instructions
404//===----------------------------------------------------------------------===//
405
406def INTERP_VEC_LOAD :  AMDGPUShaderInst <
407  (outs R600_Reg128:$dst),
408  (ins i32imm:$src0),
409  "INTERP_LOAD $src0 : $dst",
410  [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>;
411
412def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
413  let bank_swizzle = 5;
414}
415
416def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
417  let bank_swizzle = 5;
418}
419
420def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
421
422//===----------------------------------------------------------------------===//
423// Export Instructions
424//===----------------------------------------------------------------------===//
425
426def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
427
428def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
429  [SDNPHasChain, SDNPSideEffect]>;
430
431class ExportWord0 {
432  field bits<32> Word0;
433
434  bits<13> arraybase;
435  bits<2> type;
436  bits<7> gpr;
437  bits<2> elem_size;
438
439  let Word0{12-0} = arraybase;
440  let Word0{14-13} = type;
441  let Word0{21-15} = gpr;
442  let Word0{22} = 0; // RW_REL
443  let Word0{29-23} = 0; // INDEX_GPR
444  let Word0{31-30} = elem_size;
445}
446
447class ExportSwzWord1 {
448  field bits<32> Word1;
449
450  bits<3> sw_x;
451  bits<3> sw_y;
452  bits<3> sw_z;
453  bits<3> sw_w;
454  bits<1> eop;
455  bits<8> inst;
456
457  let Word1{2-0} = sw_x;
458  let Word1{5-3} = sw_y;
459  let Word1{8-6} = sw_z;
460  let Word1{11-9} = sw_w;
461}
462
463class ExportBufWord1 {
464  field bits<32> Word1;
465
466  bits<12> arraySize;
467  bits<4> compMask;
468  bits<1> eop;
469  bits<8> inst;
470
471  let Word1{11-0} = arraySize;
472  let Word1{15-12} = compMask;
473}
474
475multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
476  def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
477    (ExportInst
478        (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
479        0, 61, 0, 7, 7, 7, cf_inst, 0)
480  >;
481
482  def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
483    (ExportInst
484        (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
485        0, 61, 7, 0, 7, 7, cf_inst, 0)
486  >;
487
488  def : Pat<(int_R600_store_dummy (i32 imm:$type)),
489    (ExportInst
490        (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
491  >;
492
493  def : Pat<(int_R600_store_dummy 1),
494    (ExportInst
495        (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
496  >;
497
498  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
499    (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
500        (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
501        imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
502  >;
503
504}
505
506multiclass SteamOutputExportPattern<Instruction ExportInst,
507    bits<8> buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> {
508// Stream0
509  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
510      (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)),
511      (ExportInst R600_Reg128:$src, 0, imm:$arraybase,
512      4095, imm:$mask, buf0inst, 0)>;
513// Stream1
514  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
515      (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)),
516      (ExportInst $src, 0, imm:$arraybase,
517      4095, imm:$mask, buf1inst, 0)>;
518// Stream2
519  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
520      (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)),
521      (ExportInst $src, 0, imm:$arraybase,
522      4095, imm:$mask, buf2inst, 0)>;
523// Stream3
524  def : Pat<(int_R600_store_stream_output (v4f32 R600_Reg128:$src),
525      (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)),
526      (ExportInst $src, 0, imm:$arraybase,
527      4095, imm:$mask, buf3inst, 0)>;
528}
529
530// Export Instructions should not be duplicated by TailDuplication pass
531// (which assumes that duplicable instruction are affected by exec mask)
532let usesCustomInserter = 1, isNotDuplicable = 1 in {
533
534class ExportSwzInst : InstR600ISA<(
535    outs),
536    (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
537    RSel:$sw_x, RSel:$sw_y, RSel:$sw_z, RSel:$sw_w, i32imm:$inst,
538    i32imm:$eop),
539    !strconcat("EXPORT", " $gpr.$sw_x$sw_y$sw_z$sw_w"),
540    []>, ExportWord0, ExportSwzWord1 {
541  let elem_size = 3;
542  let Inst{31-0} = Word0;
543  let Inst{63-32} = Word1;
544  let IsExport = 1;
545}
546
547} // End usesCustomInserter = 1
548
549class ExportBufInst : InstR600ISA<(
550    outs),
551    (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
552    i32imm:$arraySize, i32imm:$compMask, i32imm:$inst, i32imm:$eop),
553    !strconcat("EXPORT", " $gpr"),
554    []>, ExportWord0, ExportBufWord1 {
555  let elem_size = 0;
556  let Inst{31-0} = Word0;
557  let Inst{63-32} = Word1;
558  let IsExport = 1;
559}
560
561//===----------------------------------------------------------------------===//
562// Control Flow Instructions
563//===----------------------------------------------------------------------===//
564
565
566def KCACHE : InstFlag<"printKCache">;
567
568class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
569(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1,
570KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1,
571i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1,
572i32imm:$COUNT, i32imm:$Enabled),
573!strconcat(OpName, " $COUNT, @$ADDR, "
574"KC0[$KCACHE_MODE0], KC1[$KCACHE_MODE1]"),
575[] >, CF_ALU_WORD0, CF_ALU_WORD1 {
576  field bits<64> Inst;
577
578  let CF_INST = inst;
579  let ALT_CONST = 0;
580  let WHOLE_QUAD_MODE = 0;
581  let BARRIER = 1;
582  let UseNamedOperandTable = 1;
583
584  let Inst{31-0} = Word0;
585  let Inst{63-32} = Word1;
586}
587
588class CF_WORD0_R600 {
589  field bits<32> Word0;
590
591  bits<32> ADDR;
592
593  let Word0 = ADDR;
594}
595
596class CF_CLAUSE_R600 <bits<7> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
597ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 {
598  field bits<64> Inst;
599  bits<4> CNT;
600
601  let CF_INST = inst;
602  let BARRIER = 1;
603  let CF_CONST = 0;
604  let VALID_PIXEL_MODE = 0;
605  let COND = 0;
606  let COUNT = CNT{2-0};
607  let CALL_COUNT = 0;
608  let COUNT_3 = CNT{3};
609  let END_OF_PROGRAM = 0;
610  let WHOLE_QUAD_MODE = 0;
611
612  let Inst{31-0} = Word0;
613  let Inst{63-32} = Word1;
614}
615
616class CF_CLAUSE_EG <bits<8> inst, dag ins, string AsmPrint> : AMDGPUInst <(outs),
617ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG {
618  field bits<64> Inst;
619
620  let CF_INST = inst;
621  let BARRIER = 1;
622  let JUMPTABLE_SEL = 0;
623  let CF_CONST = 0;
624  let VALID_PIXEL_MODE = 0;
625  let COND = 0;
626  let END_OF_PROGRAM = 0;
627
628  let Inst{31-0} = Word0;
629  let Inst{63-32} = Word1;
630}
631
632def CF_ALU : ALU_CLAUSE<8, "ALU">;
633def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
634def CF_ALU_POP_AFTER : ALU_CLAUSE<10, "ALU_POP_AFTER">;
635def CF_ALU_CONTINUE : ALU_CLAUSE<13, "ALU_CONTINUE">;
636def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">;
637def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">;
638
639def FETCH_CLAUSE : AMDGPUInst <(outs),
640(ins i32imm:$addr), "Fetch clause starting at $addr:", [] > {
641  field bits<8> Inst;
642  bits<8> num;
643  let Inst = num;
644}
645
646def ALU_CLAUSE : AMDGPUInst <(outs),
647(ins i32imm:$addr), "ALU clause starting at $addr:", [] > {
648  field bits<8> Inst;
649  bits<8> num;
650  let Inst = num;
651}
652
653def LITERALS : AMDGPUInst <(outs),
654(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
655  field bits<64> Inst;
656  bits<32> literal1;
657  bits<32> literal2;
658
659  let Inst{31-0} = literal1;
660  let Inst{63-32} = literal2;
661}
662
663def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > {
664  field bits<64> Inst;
665}
666
667let Predicates = [isR600toCayman] in {
668
669//===----------------------------------------------------------------------===//
670// Common Instructions R600, R700, Evergreen, Cayman
671//===----------------------------------------------------------------------===//
672
673def ADD : R600_2OP_Helper <0x0, "ADD", fadd>;
674// Non-IEEE MUL: 0 * anything = 0
675def MUL : R600_2OP_Helper <0x1, "MUL NON-IEEE", int_AMDGPU_mul>;
676def MUL_IEEE : R600_2OP_Helper <0x2, "MUL_IEEE", fmul>;
677// TODO: Do these actually match the regular fmin/fmax behavior?
678def MAX : R600_2OP_Helper <0x3, "MAX", AMDGPUfmax_legacy>;
679def MIN : R600_2OP_Helper <0x4, "MIN", AMDGPUfmin_legacy>;
680
681// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
682// so some of the instruction names don't match the asm string.
683// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
684def SETE : R600_2OP <
685  0x08, "SETE",
686  [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
687>;
688
689def SGT : R600_2OP <
690  0x09, "SETGT",
691  [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
692>;
693
694def SGE : R600_2OP <
695  0xA, "SETGE",
696  [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
697>;
698
699def SNE : R600_2OP <
700  0xB, "SETNE",
701  [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
702>;
703
704def SETE_DX10 : R600_2OP <
705  0xC, "SETE_DX10",
706  [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
707>;
708
709def SETGT_DX10 : R600_2OP <
710  0xD, "SETGT_DX10",
711  [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]
712>;
713
714def SETGE_DX10 : R600_2OP <
715  0xE, "SETGE_DX10",
716  [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
717>;
718
719// FIXME: This should probably be COND_ONE
720def SETNE_DX10 : R600_2OP <
721  0xF, "SETNE_DX10",
722  [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]
723>;
724
725def FRACT : R600_1OP_Helper <0x10, "FRACT", AMDGPUfract>;
726def TRUNC : R600_1OP_Helper <0x11, "TRUNC", ftrunc>;
727def CEIL : R600_1OP_Helper <0x12, "CEIL", fceil>;
728def RNDNE : R600_1OP_Helper <0x13, "RNDNE", frint>;
729def FLOOR : R600_1OP_Helper <0x14, "FLOOR", ffloor>;
730
731def MOV : R600_1OP <0x19, "MOV", []>;
732
733let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
734
735class MOV_IMM <ValueType vt, Operand immType> : AMDGPUInst <
736  (outs R600_Reg32:$dst),
737  (ins immType:$imm),
738  "",
739  []
740>;
741
742} // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
743
744def MOV_IMM_I32 : MOV_IMM<i32, i32imm>;
745def : Pat <
746  (imm:$val),
747  (MOV_IMM_I32 imm:$val)
748>;
749
750def MOV_IMM_F32 : MOV_IMM<f32, f32imm>;
751def : Pat <
752  (fpimm:$val),
753  (MOV_IMM_F32  fpimm:$val)
754>;
755
756def PRED_SETE : R600_2OP <0x20, "PRED_SETE", []>;
757def PRED_SETGT : R600_2OP <0x21, "PRED_SETGT", []>;
758def PRED_SETGE : R600_2OP <0x22, "PRED_SETGE", []>;
759def PRED_SETNE : R600_2OP <0x23, "PRED_SETNE", []>;
760
761let hasSideEffects = 1 in {
762
763def KILLGT : R600_2OP <0x2D, "KILLGT", []>;
764
765} // end hasSideEffects
766
767def AND_INT : R600_2OP_Helper <0x30, "AND_INT", and>;
768def OR_INT : R600_2OP_Helper <0x31, "OR_INT", or>;
769def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
770def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
771def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
772def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
773def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>;
774def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>;
775def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>;
776def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>;
777
778def SETE_INT : R600_2OP <
779  0x3A, "SETE_INT",
780  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
781>;
782
783def SETGT_INT : R600_2OP <
784  0x3B, "SETGT_INT",
785  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
786>;
787
788def SETGE_INT : R600_2OP <
789  0x3C, "SETGE_INT",
790  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
791>;
792
793def SETNE_INT : R600_2OP <
794  0x3D, "SETNE_INT",
795  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
796>;
797
798def SETGT_UINT : R600_2OP <
799  0x3E, "SETGT_UINT",
800  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
801>;
802
803def SETGE_UINT : R600_2OP <
804  0x3F, "SETGE_UINT",
805  [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
806>;
807
808def PRED_SETE_INT : R600_2OP <0x42, "PRED_SETE_INT", []>;
809def PRED_SETGT_INT : R600_2OP <0x43, "PRED_SETGE_INT", []>;
810def PRED_SETGE_INT : R600_2OP <0x44, "PRED_SETGE_INT", []>;
811def PRED_SETNE_INT : R600_2OP <0x45, "PRED_SETNE_INT", []>;
812
813def CNDE_INT : R600_3OP <
814  0x1C, "CNDE_INT",
815  [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
816>;
817
818def CNDGE_INT : R600_3OP <
819  0x1E, "CNDGE_INT",
820  [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]
821>;
822
823def CNDGT_INT : R600_3OP <
824  0x1D, "CNDGT_INT",
825  [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]
826>;
827
828//===----------------------------------------------------------------------===//
829// Texture instructions
830//===----------------------------------------------------------------------===//
831
832let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
833
834class R600_TEX <bits<11> inst, string opName> :
835  InstR600 <(outs R600_Reg128:$DST_GPR),
836          (ins R600_Reg128:$SRC_GPR,
837          RSel:$srcx, RSel:$srcy, RSel:$srcz, RSel:$srcw,
838          i32imm:$offsetx, i32imm:$offsety, i32imm:$offsetz,
839          RSel:$DST_SEL_X, RSel:$DST_SEL_Y, RSel:$DST_SEL_Z, RSel:$DST_SEL_W,
840          i32imm:$RESOURCE_ID, i32imm:$SAMPLER_ID,
841          CT:$COORD_TYPE_X, CT:$COORD_TYPE_Y, CT:$COORD_TYPE_Z,
842          CT:$COORD_TYPE_W),
843          !strconcat(opName,
844          " $DST_GPR.$DST_SEL_X$DST_SEL_Y$DST_SEL_Z$DST_SEL_W, "
845          "$SRC_GPR.$srcx$srcy$srcz$srcw "
846          "RID:$RESOURCE_ID SID:$SAMPLER_ID "
847          "CT:$COORD_TYPE_X$COORD_TYPE_Y$COORD_TYPE_Z$COORD_TYPE_W"),
848          [],
849          NullALU>, TEX_WORD0, TEX_WORD1, TEX_WORD2 {
850  let Inst{31-0} = Word0;
851  let Inst{63-32} = Word1;
852
853  let TEX_INST = inst{4-0};
854  let SRC_REL = 0;
855  let DST_REL = 0;
856  let LOD_BIAS = 0;
857
858  let INST_MOD = 0;
859  let FETCH_WHOLE_QUAD = 0;
860  let ALT_CONST = 0;
861  let SAMPLER_INDEX_MODE = 0;
862  let RESOURCE_INDEX_MODE = 0;
863
864  let TEXInst = 1;
865}
866
867} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
868
869
870
871def TEX_SAMPLE : R600_TEX <0x10, "TEX_SAMPLE">;
872def TEX_SAMPLE_C : R600_TEX <0x18, "TEX_SAMPLE_C">;
873def TEX_SAMPLE_L : R600_TEX <0x11, "TEX_SAMPLE_L">;
874def TEX_SAMPLE_C_L : R600_TEX <0x19, "TEX_SAMPLE_C_L">;
875def TEX_SAMPLE_LB : R600_TEX <0x12, "TEX_SAMPLE_LB">;
876def TEX_SAMPLE_C_LB : R600_TEX <0x1A, "TEX_SAMPLE_C_LB">;
877def TEX_LD : R600_TEX <0x03, "TEX_LD">;
878def TEX_LDPTR : R600_TEX <0x03, "TEX_LDPTR"> {
879  let INST_MOD = 1;
880}
881def TEX_GET_TEXTURE_RESINFO : R600_TEX <0x04, "TEX_GET_TEXTURE_RESINFO">;
882def TEX_GET_GRADIENTS_H : R600_TEX <0x07, "TEX_GET_GRADIENTS_H">;
883def TEX_GET_GRADIENTS_V : R600_TEX <0x08, "TEX_GET_GRADIENTS_V">;
884def TEX_SET_GRADIENTS_H : R600_TEX <0x0B, "TEX_SET_GRADIENTS_H">;
885def TEX_SET_GRADIENTS_V : R600_TEX <0x0C, "TEX_SET_GRADIENTS_V">;
886def TEX_SAMPLE_G : R600_TEX <0x14, "TEX_SAMPLE_G">;
887def TEX_SAMPLE_C_G : R600_TEX <0x1C, "TEX_SAMPLE_C_G">;
888
889defm : TexPattern<0, TEX_SAMPLE>;
890defm : TexPattern<1, TEX_SAMPLE_C>;
891defm : TexPattern<2, TEX_SAMPLE_L>;
892defm : TexPattern<3, TEX_SAMPLE_C_L>;
893defm : TexPattern<4, TEX_SAMPLE_LB>;
894defm : TexPattern<5, TEX_SAMPLE_C_LB>;
895defm : TexPattern<6, TEX_LD, v4i32>;
896defm : TexPattern<7, TEX_GET_TEXTURE_RESINFO, v4i32>;
897defm : TexPattern<8, TEX_GET_GRADIENTS_H>;
898defm : TexPattern<9, TEX_GET_GRADIENTS_V>;
899defm : TexPattern<10, TEX_LDPTR, v4i32>;
900
901//===----------------------------------------------------------------------===//
902// Helper classes for common instructions
903//===----------------------------------------------------------------------===//
904
905class MUL_LIT_Common <bits<5> inst> : R600_3OP <
906  inst, "MUL_LIT",
907  []
908>;
909
910class MULADD_Common <bits<5> inst> : R600_3OP <
911  inst, "MULADD",
912  []
913>;
914
915class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
916  inst, "MULADD_IEEE",
917  [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
918>;
919
920class FMA_Common <bits<5> inst> : R600_3OP <
921  inst, "FMA",
922  [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
923>;
924
925class CNDE_Common <bits<5> inst> : R600_3OP <
926  inst, "CNDE",
927  [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
928>;
929
930class CNDGT_Common <bits<5> inst> : R600_3OP <
931  inst, "CNDGT",
932  [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
933> {
934  let Itinerary = VecALU;
935}
936
937class CNDGE_Common <bits<5> inst> : R600_3OP <
938  inst, "CNDGE",
939  [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
940> {
941  let Itinerary = VecALU;
942}
943
944
945let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"  in {
946class R600_VEC2OP<list<dag> pattern> : InstR600 <(outs R600_Reg32:$dst), (ins
947// Slot X
948   UEM:$update_exec_mask_X, UP:$update_pred_X, WRITE:$write_X,
949   OMOD:$omod_X, REL:$dst_rel_X, CLAMP:$clamp_X,
950   R600_TReg32_X:$src0_X, NEG:$src0_neg_X, REL:$src0_rel_X, ABS:$src0_abs_X, SEL:$src0_sel_X,
951   R600_TReg32_X:$src1_X, NEG:$src1_neg_X, REL:$src1_rel_X, ABS:$src1_abs_X, SEL:$src1_sel_X,
952   R600_Pred:$pred_sel_X,
953// Slot Y
954   UEM:$update_exec_mask_Y, UP:$update_pred_Y, WRITE:$write_Y,
955   OMOD:$omod_Y, REL:$dst_rel_Y, CLAMP:$clamp_Y,
956   R600_TReg32_Y:$src0_Y, NEG:$src0_neg_Y, REL:$src0_rel_Y, ABS:$src0_abs_Y, SEL:$src0_sel_Y,
957   R600_TReg32_Y:$src1_Y, NEG:$src1_neg_Y, REL:$src1_rel_Y, ABS:$src1_abs_Y, SEL:$src1_sel_Y,
958   R600_Pred:$pred_sel_Y,
959// Slot Z
960   UEM:$update_exec_mask_Z, UP:$update_pred_Z, WRITE:$write_Z,
961   OMOD:$omod_Z, REL:$dst_rel_Z, CLAMP:$clamp_Z,
962   R600_TReg32_Z:$src0_Z, NEG:$src0_neg_Z, REL:$src0_rel_Z, ABS:$src0_abs_Z, SEL:$src0_sel_Z,
963   R600_TReg32_Z:$src1_Z, NEG:$src1_neg_Z, REL:$src1_rel_Z, ABS:$src1_abs_Z, SEL:$src1_sel_Z,
964   R600_Pred:$pred_sel_Z,
965// Slot W
966   UEM:$update_exec_mask_W, UP:$update_pred_W, WRITE:$write_W,
967   OMOD:$omod_W, REL:$dst_rel_W, CLAMP:$clamp_W,
968   R600_TReg32_W:$src0_W, NEG:$src0_neg_W, REL:$src0_rel_W, ABS:$src0_abs_W, SEL:$src0_sel_W,
969   R600_TReg32_W:$src1_W, NEG:$src1_neg_W, REL:$src1_rel_W, ABS:$src1_abs_W, SEL:$src1_sel_W,
970   R600_Pred:$pred_sel_W,
971   LITERAL:$literal0, LITERAL:$literal1),
972  "",
973  pattern,
974  AnyALU> {
975
976  let UseNamedOperandTable = 1;
977
978}
979}
980
981def DOT_4 : R600_VEC2OP<[(set R600_Reg32:$dst, (DOT4
982  R600_TReg32_X:$src0_X, R600_TReg32_X:$src1_X,
983  R600_TReg32_Y:$src0_Y, R600_TReg32_Y:$src1_Y,
984  R600_TReg32_Z:$src0_Z, R600_TReg32_Z:$src1_Z,
985  R600_TReg32_W:$src0_W, R600_TReg32_W:$src1_W))]>;
986
987
988class DOT4_Common <bits<11> inst> : R600_2OP <inst, "DOT4", []>;
989
990
991let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
992multiclass CUBE_Common <bits<11> inst> {
993
994  def _pseudo : InstR600 <
995    (outs R600_Reg128:$dst),
996    (ins R600_Reg128:$src0),
997    "CUBE $dst $src0",
998    [(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
999    VecALU
1000  > {
1001    let isPseudo = 1;
1002    let UseNamedOperandTable = 1;
1003  }
1004
1005  def _real : R600_2OP <inst, "CUBE", []>;
1006}
1007} // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1008
1009class EXP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1010  inst, "EXP_IEEE", fexp2
1011> {
1012  let Itinerary = TransALU;
1013}
1014
1015class FLT_TO_INT_Common <bits<11> inst> : R600_1OP_Helper <
1016  inst, "FLT_TO_INT", fp_to_sint
1017> {
1018  let Itinerary = TransALU;
1019}
1020
1021class INT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1022  inst, "INT_TO_FLT", sint_to_fp
1023> {
1024  let Itinerary = TransALU;
1025}
1026
1027class FLT_TO_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1028  inst, "FLT_TO_UINT", fp_to_uint
1029> {
1030  let Itinerary = TransALU;
1031}
1032
1033class UINT_TO_FLT_Common <bits<11> inst> : R600_1OP_Helper <
1034  inst, "UINT_TO_FLT", uint_to_fp
1035> {
1036  let Itinerary = TransALU;
1037}
1038
1039class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
1040  inst, "LOG_CLAMPED", []
1041>;
1042
1043class LOG_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1044  inst, "LOG_IEEE", flog2
1045> {
1046  let Itinerary = TransALU;
1047}
1048
1049class LSHL_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHL", shl>;
1050class LSHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "LSHR", srl>;
1051class ASHR_Common <bits<11> inst> : R600_2OP_Helper <inst, "ASHR", sra>;
1052class MULHI_INT_Common <bits<11> inst> : R600_2OP_Helper <
1053  inst, "MULHI_INT", mulhs
1054> {
1055  let Itinerary = TransALU;
1056}
1057class MULHI_UINT_Common <bits<11> inst> : R600_2OP_Helper <
1058  inst, "MULHI", mulhu
1059> {
1060  let Itinerary = TransALU;
1061}
1062class MULLO_INT_Common <bits<11> inst> : R600_2OP_Helper <
1063  inst, "MULLO_INT", mul
1064> {
1065  let Itinerary = TransALU;
1066}
1067class MULLO_UINT_Common <bits<11> inst> : R600_2OP <inst, "MULLO_UINT", []> {
1068  let Itinerary = TransALU;
1069}
1070
1071class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
1072  inst, "RECIP_CLAMPED", []
1073> {
1074  let Itinerary = TransALU;
1075}
1076
1077class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
1078  inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))]
1079> {
1080  let Itinerary = TransALU;
1081}
1082
1083class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
1084  inst, "RECIP_UINT", AMDGPUurecip
1085> {
1086  let Itinerary = TransALU;
1087}
1088
1089// Clamped to maximum.
1090class RECIPSQRT_CLAMPED_Common <bits<11> inst> : R600_1OP_Helper <
1091  inst, "RECIPSQRT_CLAMPED", AMDGPUrsq_clamped
1092> {
1093  let Itinerary = TransALU;
1094}
1095
1096class RECIPSQRT_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
1097  inst, "RECIPSQRT_IEEE", AMDGPUrsq_legacy
1098> {
1099  let Itinerary = TransALU;
1100}
1101
1102// TODO: There is also RECIPSQRT_FF which clamps to zero.
1103
1104class SIN_Common <bits<11> inst> : R600_1OP <
1105  inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1106  let Trig = 1;
1107  let Itinerary = TransALU;
1108}
1109
1110class COS_Common <bits<11> inst> : R600_1OP <
1111  inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1112  let Trig = 1;
1113  let Itinerary = TransALU;
1114}
1115
1116def CLAMP_R600 :  CLAMP <R600_Reg32>;
1117def FABS_R600 : FABS<R600_Reg32>;
1118def FNEG_R600 : FNEG<R600_Reg32>;
1119
1120//===----------------------------------------------------------------------===//
1121// Helper patterns for complex intrinsics
1122//===----------------------------------------------------------------------===//
1123
1124// FIXME: Should be predicated on unsafe fp math.
1125multiclass DIV_Common <InstR600 recip_ieee> {
1126def : Pat<
1127  (int_AMDGPU_div f32:$src0, f32:$src1),
1128  (MUL_IEEE $src0, (recip_ieee $src1))
1129>;
1130
1131def : Pat<
1132  (fdiv f32:$src0, f32:$src1),
1133  (MUL_IEEE $src0, (recip_ieee $src1))
1134>;
1135
1136def : RcpPat<recip_ieee, f32>;
1137}
1138
1139class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
1140  : Pat <
1141  (int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
1142  (exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
1143>;
1144
1145// FROUND pattern
1146class FROUNDPat<Instruction CNDGE, Instruction CNDGT> : Pat <
1147  (AMDGPUround f32:$x),
1148  (CNDGE $x,
1149  (CNDGE (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x)),
1150  (CNDGT (ADD (FNEG_R600 (f32 HALF)), (FRACT $x)), (CEIL $x), (FLOOR $x))
1151  )
1152>;
1153
1154
1155//===----------------------------------------------------------------------===//
1156// R600 / R700 Instructions
1157//===----------------------------------------------------------------------===//
1158
1159let Predicates = [isR600] in {
1160
1161  def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
1162  def MULADD_r600 : MULADD_Common<0x10>;
1163  def MULADD_IEEE_r600 : MULADD_IEEE_Common<0x14>;
1164  def CNDE_r600 : CNDE_Common<0x18>;
1165  def CNDGT_r600 : CNDGT_Common<0x19>;
1166  def CNDGE_r600 : CNDGE_Common<0x1A>;
1167  def DOT4_r600 : DOT4_Common<0x50>;
1168  defm CUBE_r600 : CUBE_Common<0x52>;
1169  def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>;
1170  def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>;
1171  def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>;
1172  def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>;
1173  def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>;
1174  def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>;
1175  def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
1176  def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
1177  def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
1178  def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
1179  def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
1180  def SIN_r600 : SIN_Common<0x6E>;
1181  def COS_r600 : COS_Common<0x6F>;
1182  def ASHR_r600 : ASHR_Common<0x70>;
1183  def LSHR_r600 : LSHR_Common<0x71>;
1184  def LSHL_r600 : LSHL_Common<0x72>;
1185  def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
1186  def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
1187  def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
1188  def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
1189  def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
1190
1191  defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
1192  def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
1193  def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
1194
1195  def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
1196  defm : RsqPat<RECIPSQRT_IEEE_r600, f32>;
1197
1198  def : FROUNDPat <CNDGE_r600, CNDGT_r600>;
1199
1200  def R600_ExportSwz : ExportSwzInst {
1201    let Word1{20-17} = 0; // BURST_COUNT
1202    let Word1{21} = eop;
1203    let Word1{22} = 0; // VALID_PIXEL_MODE
1204    let Word1{30-23} = inst;
1205    let Word1{31} = 1; // BARRIER
1206  }
1207  defm : ExportPattern<R600_ExportSwz, 39>;
1208
1209  def R600_ExportBuf : ExportBufInst {
1210    let Word1{20-17} = 0; // BURST_COUNT
1211    let Word1{21} = eop;
1212    let Word1{22} = 0; // VALID_PIXEL_MODE
1213    let Word1{30-23} = inst;
1214    let Word1{31} = 1; // BARRIER
1215  }
1216  defm : SteamOutputExportPattern<R600_ExportBuf, 0x20, 0x21, 0x22, 0x23>;
1217
1218  def CF_TC_R600 : CF_CLAUSE_R600<1, (ins i32imm:$ADDR, i32imm:$CNT),
1219  "TEX $CNT @$ADDR"> {
1220    let POP_COUNT = 0;
1221  }
1222  def CF_VC_R600 : CF_CLAUSE_R600<2, (ins i32imm:$ADDR, i32imm:$CNT),
1223  "VTX $CNT @$ADDR"> {
1224    let POP_COUNT = 0;
1225  }
1226  def WHILE_LOOP_R600 : CF_CLAUSE_R600<6, (ins i32imm:$ADDR),
1227  "LOOP_START_DX10 @$ADDR"> {
1228    let POP_COUNT = 0;
1229    let CNT = 0;
1230  }
1231  def END_LOOP_R600 : CF_CLAUSE_R600<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> {
1232    let POP_COUNT = 0;
1233    let CNT = 0;
1234  }
1235  def LOOP_BREAK_R600 : CF_CLAUSE_R600<9, (ins i32imm:$ADDR),
1236  "LOOP_BREAK @$ADDR"> {
1237    let POP_COUNT = 0;
1238    let CNT = 0;
1239  }
1240  def CF_CONTINUE_R600 : CF_CLAUSE_R600<8, (ins i32imm:$ADDR),
1241  "CONTINUE @$ADDR"> {
1242    let POP_COUNT = 0;
1243    let CNT = 0;
1244  }
1245  def CF_JUMP_R600 : CF_CLAUSE_R600<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1246  "JUMP @$ADDR POP:$POP_COUNT"> {
1247    let CNT = 0;
1248  }
1249  def CF_PUSH_ELSE_R600 : CF_CLAUSE_R600<12, (ins i32imm:$ADDR),
1250  "PUSH_ELSE @$ADDR"> {
1251    let CNT = 0;
1252  }
1253  def CF_ELSE_R600 : CF_CLAUSE_R600<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1254  "ELSE @$ADDR POP:$POP_COUNT"> {
1255    let CNT = 0;
1256  }
1257  def CF_CALL_FS_R600 : CF_CLAUSE_R600<19, (ins), "CALL_FS"> {
1258    let ADDR = 0;
1259    let CNT = 0;
1260    let POP_COUNT = 0;
1261  }
1262  def POP_R600 : CF_CLAUSE_R600<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT),
1263  "POP @$ADDR POP:$POP_COUNT"> {
1264    let CNT = 0;
1265  }
1266  def CF_END_R600 : CF_CLAUSE_R600<0, (ins), "CF_END"> {
1267    let CNT = 0;
1268    let POP_COUNT = 0;
1269    let ADDR = 0;
1270    let END_OF_PROGRAM = 1;
1271  }
1272
1273}
1274
1275
1276//===----------------------------------------------------------------------===//
1277// Regist loads and stores - for indirect addressing
1278//===----------------------------------------------------------------------===//
1279
1280defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
1281
1282
1283//===----------------------------------------------------------------------===//
1284// Pseudo instructions
1285//===----------------------------------------------------------------------===//
1286
1287let isPseudo = 1 in {
1288
1289def PRED_X : InstR600 <
1290  (outs R600_Predicate_Bit:$dst),
1291  (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1292  "", [], NullALU> {
1293  let FlagOperandIdx = 3;
1294}
1295
1296let isTerminator = 1, isBranch = 1 in {
1297def JUMP_COND : InstR600 <
1298          (outs),
1299          (ins brtarget:$target, R600_Predicate_Bit:$p),
1300          "JUMP $target ($p)",
1301          [], AnyALU
1302  >;
1303
1304def JUMP : InstR600 <
1305          (outs),
1306          (ins brtarget:$target),
1307          "JUMP $target",
1308          [], AnyALU
1309  >
1310{
1311  let isPredicable = 1;
1312  let isBarrier = 1;
1313}
1314
1315}  // End isTerminator = 1, isBranch = 1
1316
1317let usesCustomInserter = 1 in {
1318
1319let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1320
1321def MASK_WRITE : AMDGPUShaderInst <
1322    (outs),
1323    (ins R600_Reg32:$src),
1324    "MASK_WRITE $src",
1325    []
1326>;
1327
1328} // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1329
1330
1331def TXD: InstR600 <
1332  (outs R600_Reg128:$dst),
1333  (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1334       i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1335  "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1336  [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1337                     imm:$resourceId, imm:$samplerId, imm:$textureTarget))],
1338  NullALU > {
1339  let TEXInst = 1;
1340}
1341
1342def TXD_SHADOW: InstR600 <
1343  (outs R600_Reg128:$dst),
1344  (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1345       i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1346  "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1347  [(set v4f32:$dst, (int_AMDGPU_txd v4f32:$src0, v4f32:$src1, v4f32:$src2,
1348        imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))],
1349   NullALU
1350> {
1351  let TEXInst = 1;
1352}
1353} // End isPseudo = 1
1354} // End usesCustomInserter = 1
1355
1356
1357//===----------------------------------------------------------------------===//
1358// Constant Buffer Addressing Support
1359//===----------------------------------------------------------------------===//
1360
1361let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"  in {
1362def CONST_COPY : Instruction {
1363  let OutOperandList = (outs R600_Reg32:$dst);
1364  let InOperandList = (ins i32imm:$src);
1365  let Pattern =
1366      [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
1367  let AsmString = "CONST_COPY";
1368  let hasSideEffects = 0;
1369  let isAsCheapAsAMove = 1;
1370  let Itinerary = NullALU;
1371}
1372} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1373
1374def TEX_VTX_CONSTBUF :
1375  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "VTX_READ_eg $dst, $ptr",
1376      [(set v4i32:$dst, (CONST_ADDRESS ADDRGA_VAR_OFFSET:$ptr, (i32 imm:$BUFFER_ID)))]>,
1377  VTX_WORD1_GPR, VTX_WORD0_eg {
1378
1379  let VC_INST = 0;
1380  let FETCH_TYPE = 2;
1381  let FETCH_WHOLE_QUAD = 0;
1382  let SRC_REL = 0;
1383  let SRC_SEL_X = 0;
1384  let DST_REL = 0;
1385  let USE_CONST_FIELDS = 0;
1386  let NUM_FORMAT_ALL = 2;
1387  let FORMAT_COMP_ALL = 1;
1388  let SRF_MODE_ALL = 1;
1389  let MEGA_FETCH_COUNT = 16;
1390  let DST_SEL_X        = 0;
1391  let DST_SEL_Y        = 1;
1392  let DST_SEL_Z        = 2;
1393  let DST_SEL_W        = 3;
1394  let DATA_FORMAT      = 35;
1395
1396  let Inst{31-0} = Word0;
1397  let Inst{63-32} = Word1;
1398
1399// LLVM can only encode 64-bit instructions, so these fields are manually
1400// encoded in R600CodeEmitter
1401//
1402// bits<16> OFFSET;
1403// bits<2>  ENDIAN_SWAP = 0;
1404// bits<1>  CONST_BUF_NO_STRIDE = 0;
1405// bits<1>  MEGA_FETCH = 0;
1406// bits<1>  ALT_CONST = 0;
1407// bits<2>  BUFFER_INDEX_MODE = 0;
1408
1409
1410
1411// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1412// is done in R600CodeEmitter
1413//
1414// Inst{79-64} = OFFSET;
1415// Inst{81-80} = ENDIAN_SWAP;
1416// Inst{82}    = CONST_BUF_NO_STRIDE;
1417// Inst{83}    = MEGA_FETCH;
1418// Inst{84}    = ALT_CONST;
1419// Inst{86-85} = BUFFER_INDEX_MODE;
1420// Inst{95-86} = 0; Reserved
1421
1422// VTX_WORD3 (Padding)
1423//
1424// Inst{127-96} = 0;
1425  let VTXInst = 1;
1426}
1427
1428def TEX_VTX_TEXBUF:
1429  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
1430      [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
1431VTX_WORD1_GPR, VTX_WORD0_eg {
1432
1433let VC_INST = 0;
1434let FETCH_TYPE = 2;
1435let FETCH_WHOLE_QUAD = 0;
1436let SRC_REL = 0;
1437let SRC_SEL_X = 0;
1438let DST_REL = 0;
1439let USE_CONST_FIELDS = 1;
1440let NUM_FORMAT_ALL = 0;
1441let FORMAT_COMP_ALL = 0;
1442let SRF_MODE_ALL = 1;
1443let MEGA_FETCH_COUNT = 16;
1444let DST_SEL_X        = 0;
1445let DST_SEL_Y        = 1;
1446let DST_SEL_Z        = 2;
1447let DST_SEL_W        = 3;
1448let DATA_FORMAT      = 0;
1449
1450let Inst{31-0} = Word0;
1451let Inst{63-32} = Word1;
1452
1453// LLVM can only encode 64-bit instructions, so these fields are manually
1454// encoded in R600CodeEmitter
1455//
1456// bits<16> OFFSET;
1457// bits<2>  ENDIAN_SWAP = 0;
1458// bits<1>  CONST_BUF_NO_STRIDE = 0;
1459// bits<1>  MEGA_FETCH = 0;
1460// bits<1>  ALT_CONST = 0;
1461// bits<2>  BUFFER_INDEX_MODE = 0;
1462
1463
1464
1465// VTX_WORD2 (LLVM can only encode 64-bit instructions, so WORD2 encoding
1466// is done in R600CodeEmitter
1467//
1468// Inst{79-64} = OFFSET;
1469// Inst{81-80} = ENDIAN_SWAP;
1470// Inst{82}    = CONST_BUF_NO_STRIDE;
1471// Inst{83}    = MEGA_FETCH;
1472// Inst{84}    = ALT_CONST;
1473// Inst{86-85} = BUFFER_INDEX_MODE;
1474// Inst{95-86} = 0; Reserved
1475
1476// VTX_WORD3 (Padding)
1477//
1478// Inst{127-96} = 0;
1479  let VTXInst = 1;
1480}
1481
1482//===---------------------------------------------------------------------===//
1483// Flow and Program control Instructions
1484//===---------------------------------------------------------------------===//
1485class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
1486: Instruction {
1487
1488     let Namespace = "AMDGPU";
1489     dag OutOperandList = outs;
1490     dag InOperandList = ins;
1491     let Pattern = pattern;
1492     let AsmString = !strconcat(asmstr, "\n");
1493     let isPseudo = 1;
1494     let Itinerary = NullALU;
1495     bit hasIEEEFlag = 0;
1496     bit hasZeroOpFlag = 0;
1497     let mayLoad = 0;
1498     let mayStore = 0;
1499     let hasSideEffects = 0;
1500     let isCodeGenOnly = 1;
1501}
1502
1503multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {
1504    def _i32 : ILFormat<(outs),
1505  (ins brtarget:$target, rci:$src0),
1506        "; i32 Pseudo branch instruction",
1507  [(Op bb:$target, (i32 rci:$src0))]>;
1508    def _f32 : ILFormat<(outs),
1509  (ins brtarget:$target, rcf:$src0),
1510        "; f32 Pseudo branch instruction",
1511  [(Op bb:$target, (f32 rcf:$src0))]>;
1512}
1513
1514// Only scalar types should generate flow control
1515multiclass BranchInstr<string name> {
1516  def _i32 : ILFormat<(outs), (ins R600_Reg32:$src),
1517      !strconcat(name, " $src"), []>;
1518  def _f32 : ILFormat<(outs), (ins R600_Reg32:$src),
1519      !strconcat(name, " $src"), []>;
1520}
1521// Only scalar types should generate flow control
1522multiclass BranchInstr2<string name> {
1523  def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1524      !strconcat(name, " $src0, $src1"), []>;
1525  def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1526      !strconcat(name, " $src0, $src1"), []>;
1527}
1528
1529//===---------------------------------------------------------------------===//
1530// Custom Inserter for Branches and returns, this eventually will be a
1531// separate pass
1532//===---------------------------------------------------------------------===//
1533let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
1534  def BRANCH : ILFormat<(outs), (ins brtarget:$target),
1535      "; Pseudo unconditional branch instruction",
1536      [(br bb:$target)]>;
1537  defm BRANCH_COND : BranchConditional<IL_brcond, R600_Reg32, R600_Reg32>;
1538}
1539
1540//===---------------------------------------------------------------------===//
1541// Return instruction
1542//===---------------------------------------------------------------------===//
1543let isTerminator = 1, isReturn = 1, hasCtrlDep = 1,
1544    usesCustomInserter = 1 in {
1545  def RETURN          : ILFormat<(outs), (ins variable_ops),
1546      "RETURN", [(IL_retflag)]>;
1547}
1548
1549//===----------------------------------------------------------------------===//
1550// Branch Instructions
1551//===----------------------------------------------------------------------===//
1552
1553def IF_PREDICATE_SET  : ILFormat<(outs), (ins R600_Reg32:$src),
1554  "IF_PREDICATE_SET $src", []>;
1555
1556let isTerminator=1 in {
1557  def BREAK       : ILFormat< (outs), (ins),
1558      "BREAK", []>;
1559  def CONTINUE    : ILFormat< (outs), (ins),
1560      "CONTINUE", []>;
1561  def DEFAULT     : ILFormat< (outs), (ins),
1562      "DEFAULT", []>;
1563  def ELSE        : ILFormat< (outs), (ins),
1564      "ELSE", []>;
1565  def ENDSWITCH   : ILFormat< (outs), (ins),
1566      "ENDSWITCH", []>;
1567  def ENDMAIN     : ILFormat< (outs), (ins),
1568      "ENDMAIN", []>;
1569  def END         : ILFormat< (outs), (ins),
1570      "END", []>;
1571  def ENDFUNC     : ILFormat< (outs), (ins),
1572      "ENDFUNC", []>;
1573  def ENDIF       : ILFormat< (outs), (ins),
1574      "ENDIF", []>;
1575  def WHILELOOP   : ILFormat< (outs), (ins),
1576      "WHILE", []>;
1577  def ENDLOOP     : ILFormat< (outs), (ins),
1578      "ENDLOOP", []>;
1579  def FUNC        : ILFormat< (outs), (ins),
1580      "FUNC", []>;
1581  def RETDYN      : ILFormat< (outs), (ins),
1582      "RET_DYN", []>;
1583  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1584  defm IF_LOGICALNZ  : BranchInstr<"IF_LOGICALNZ">;
1585  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1586  defm IF_LOGICALZ   : BranchInstr<"IF_LOGICALZ">;
1587  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1588  defm BREAK_LOGICALNZ : BranchInstr<"BREAK_LOGICALNZ">;
1589  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1590  defm BREAK_LOGICALZ : BranchInstr<"BREAK_LOGICALZ">;
1591  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1592  defm CONTINUE_LOGICALNZ : BranchInstr<"CONTINUE_LOGICALNZ">;
1593  // This opcode has custom swizzle pattern encoded in Swizzle Encoder
1594  defm CONTINUE_LOGICALZ : BranchInstr<"CONTINUE_LOGICALZ">;
1595  defm IFC         : BranchInstr2<"IFC">;
1596  defm BREAKC      : BranchInstr2<"BREAKC">;
1597  defm CONTINUEC   : BranchInstr2<"CONTINUEC">;
1598}
1599
1600//===----------------------------------------------------------------------===//
1601// Indirect addressing pseudo instructions
1602//===----------------------------------------------------------------------===//
1603
1604let isPseudo = 1 in {
1605
1606class ExtractVertical <RegisterClass vec_rc> : InstR600 <
1607  (outs R600_Reg32:$dst),
1608  (ins vec_rc:$vec, R600_Reg32:$index), "",
1609  [],
1610  AnyALU
1611>;
1612
1613let Constraints = "$dst = $vec" in {
1614
1615class InsertVertical <RegisterClass vec_rc> : InstR600 <
1616  (outs vec_rc:$dst),
1617  (ins vec_rc:$vec, R600_Reg32:$value, R600_Reg32:$index), "",
1618  [],
1619  AnyALU
1620>;
1621
1622} // End Constraints = "$dst = $vec"
1623
1624} // End isPseudo = 1
1625
1626def R600_EXTRACT_ELT_V2 : ExtractVertical <R600_Reg64Vertical>;
1627def R600_EXTRACT_ELT_V4 : ExtractVertical <R600_Reg128Vertical>;
1628
1629def R600_INSERT_ELT_V2 : InsertVertical <R600_Reg64Vertical>;
1630def R600_INSERT_ELT_V4 : InsertVertical <R600_Reg128Vertical>;
1631
1632class ExtractVerticalPat <Instruction inst, ValueType vec_ty,
1633                          ValueType scalar_ty> : Pat <
1634  (scalar_ty (extractelt vec_ty:$vec, i32:$index)),
1635  (inst $vec, $index)
1636>;
1637
1638def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2i32, i32>;
1639def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
1640def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4i32, i32>;
1641def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
1642
1643class InsertVerticalPat <Instruction inst, ValueType vec_ty,
1644                         ValueType scalar_ty> : Pat <
1645  (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)),
1646  (inst $vec, $value, $index)
1647>;
1648
1649def : InsertVerticalPat <R600_INSERT_ELT_V2, v2i32, i32>;
1650def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
1651def : InsertVerticalPat <R600_INSERT_ELT_V4, v4i32, i32>;
1652def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f32>;
1653
1654//===----------------------------------------------------------------------===//
1655// ISel Patterns
1656//===----------------------------------------------------------------------===//
1657
1658// CND*_INT Pattterns for f32 True / False values
1659
1660class CND_INT_f32 <InstR600 cnd, CondCode cc> : Pat <
1661  (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
1662  (cnd $src0, $src1, $src2)
1663>;
1664
1665def : CND_INT_f32 <CNDE_INT,  SETEQ>;
1666def : CND_INT_f32 <CNDGT_INT, SETGT>;
1667def : CND_INT_f32 <CNDGE_INT, SETGE>;
1668
1669//CNDGE_INT extra pattern
1670def : Pat <
1671  (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),
1672  (CNDGE_INT $src0, $src1, $src2)
1673>;
1674
1675// KIL Patterns
1676def KILP : Pat <
1677  (int_AMDGPU_kilp),
1678  (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
1679>;
1680
1681def KIL : Pat <
1682  (int_AMDGPU_kill f32:$src0),
1683  (MASK_WRITE (KILLGT (f32 ZERO), $src0))
1684>;
1685
1686def : Extract_Element <f32, v4f32, 0, sub0>;
1687def : Extract_Element <f32, v4f32, 1, sub1>;
1688def : Extract_Element <f32, v4f32, 2, sub2>;
1689def : Extract_Element <f32, v4f32, 3, sub3>;
1690
1691def : Insert_Element <f32, v4f32, 0, sub0>;
1692def : Insert_Element <f32, v4f32, 1, sub1>;
1693def : Insert_Element <f32, v4f32, 2, sub2>;
1694def : Insert_Element <f32, v4f32, 3, sub3>;
1695
1696def : Extract_Element <i32, v4i32, 0, sub0>;
1697def : Extract_Element <i32, v4i32, 1, sub1>;
1698def : Extract_Element <i32, v4i32, 2, sub2>;
1699def : Extract_Element <i32, v4i32, 3, sub3>;
1700
1701def : Insert_Element <i32, v4i32, 0, sub0>;
1702def : Insert_Element <i32, v4i32, 1, sub1>;
1703def : Insert_Element <i32, v4i32, 2, sub2>;
1704def : Insert_Element <i32, v4i32, 3, sub3>;
1705
1706def : Extract_Element <f32, v2f32, 0, sub0>;
1707def : Extract_Element <f32, v2f32, 1, sub1>;
1708
1709def : Insert_Element <f32, v2f32, 0, sub0>;
1710def : Insert_Element <f32, v2f32, 1, sub1>;
1711
1712def : Extract_Element <i32, v2i32, 0, sub0>;
1713def : Extract_Element <i32, v2i32, 1, sub1>;
1714
1715def : Insert_Element <i32, v2i32, 0, sub0>;
1716def : Insert_Element <i32, v2i32, 1, sub1>;
1717
1718// bitconvert patterns
1719
1720def : BitConvert <i32, f32, R600_Reg32>;
1721def : BitConvert <f32, i32, R600_Reg32>;
1722def : BitConvert <v2f32, v2i32, R600_Reg64>;
1723def : BitConvert <v2i32, v2f32, R600_Reg64>;
1724def : BitConvert <v4f32, v4i32, R600_Reg128>;
1725def : BitConvert <v4i32, v4f32, R600_Reg128>;
1726
1727// DWORDADDR pattern
1728def : DwordAddrPat  <i32, R600_Reg32>;
1729
1730} // End isR600toCayman Predicate
1731
1732let Predicates = [isR600] in {
1733// Intrinsic patterns
1734defm : Expand24IBitOps<MULLO_INT_r600, ADD_INT>;
1735defm : Expand24UBitOps<MULLO_UINT_r600, ADD_INT>;
1736} // End isR600
1737
1738def getLDSNoRetOp : InstrMapping {
1739  let FilterClass = "R600_LDS_1A1D";
1740  let RowFields = ["BaseOp"];
1741  let ColFields = ["DisableEncoding"];
1742  let KeyCol = ["$dst"];
1743  let ValueCols = [[""""]];
1744}
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