source: icGREP/icgrep-devel/llvm-3.5.0.src/lib/Target/R600/SIInstrInfo.td @ 4574

Last change on this file since 4574 was 4574, checked in by cameron, 4 years ago

Updating to LLVM 3.6

File size: 70.8 KB
Line 
1//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class vop {
11  field bits<9> SI3;
12  field bits<10> VI3;
13}
14
15class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
16  field bits<8> SI = si;
17  field bits<8> VI = vi;
18
19  field bits<9>  SI3 = {0, si{7-0}};
20  field bits<10> VI3 = {0, 0, vi{7-0}};
21}
22
23class vop1 <bits<8> si, bits<8> vi = si> : vop {
24  field bits<8> SI = si;
25  field bits<8> VI = vi;
26
27  field bits<9>  SI3 = {1, 1, si{6-0}};
28  field bits<10> VI3 = !add(0x140, vi);
29}
30
31class vop2 <bits<6> si, bits<6> vi = si> : vop {
32  field bits<6> SI = si;
33  field bits<6> VI = vi;
34
35  field bits<9>  SI3 = {1, 0, 0, si{5-0}};
36  field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
37}
38
39// Specify a VOP2 opcode for SI and VOP3 opcode for VI
40// that doesn't have VOP2 encoding on VI
41class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
42  let VI3 = vi;
43}
44
45class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
46  let SI3 = si;
47  let VI3 = vi;
48}
49
50class sop1 <bits<8> si, bits<8> vi = si> {
51  field bits<8> SI = si;
52  field bits<8> VI = vi;
53}
54
55class sop2 <bits<7> si, bits<7> vi = si> {
56  field bits<7> SI = si;
57  field bits<7> VI = vi;
58}
59
60class sopk <bits<5> si, bits<5> vi = si> {
61  field bits<5> SI = si;
62  field bits<5> VI = vi;
63}
64
65// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
66// in AMDGPUInstrInfo.cpp
67def SISubtarget {
68  int NONE = -1;
69  int SI = 0;
70  int VI = 1;
71}
72
73//===----------------------------------------------------------------------===//
74// SI DAG Nodes
75//===----------------------------------------------------------------------===//
76
77def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
78  SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
79                      [SDNPMayLoad, SDNPMemOperand]
80>;
81
82def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
83  SDTypeProfile<0, 13,
84    [SDTCisVT<0, v4i32>,   // rsrc(SGPR)
85     SDTCisVT<1, iAny>,   // vdata(VGPR)
86     SDTCisVT<2, i32>,    // num_channels(imm)
87     SDTCisVT<3, i32>,    // vaddr(VGPR)
88     SDTCisVT<4, i32>,    // soffset(SGPR)
89     SDTCisVT<5, i32>,    // inst_offset(imm)
90     SDTCisVT<6, i32>,    // dfmt(imm)
91     SDTCisVT<7, i32>,    // nfmt(imm)
92     SDTCisVT<8, i32>,    // offen(imm)
93     SDTCisVT<9, i32>,    // idxen(imm)
94     SDTCisVT<10, i32>,   // glc(imm)
95     SDTCisVT<11, i32>,   // slc(imm)
96     SDTCisVT<12, i32>    // tfe(imm)
97    ]>,
98  [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
99>;
100
101def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
102  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
103                       SDTCisVT<3, i32>]>
104>;
105
106class SDSample<string opcode> : SDNode <opcode,
107  SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
108                       SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
109>;
110
111def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
112def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
113def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
114def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
115
116def SIconstdata_ptr : SDNode<
117  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
118>;
119
120// Transformation function, extract the lower 32bit of a 64bit immediate
121def LO32 : SDNodeXForm<imm, [{
122  return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
123}]>;
124
125def LO32f : SDNodeXForm<fpimm, [{
126  APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
127  return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
128}]>;
129
130// Transformation function, extract the upper 32bit of a 64bit immediate
131def HI32 : SDNodeXForm<imm, [{
132  return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
133}]>;
134
135def HI32f : SDNodeXForm<fpimm, [{
136  APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
137  return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
138}]>;
139
140def IMM8bitDWORD : PatLeaf <(imm),
141  [{return (N->getZExtValue() & ~0x3FC) == 0;}]
142>;
143
144def as_dword_i32imm : SDNodeXForm<imm, [{
145  return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
146}]>;
147
148def as_i1imm : SDNodeXForm<imm, [{
149  return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
150}]>;
151
152def as_i8imm : SDNodeXForm<imm, [{
153  return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
154}]>;
155
156def as_i16imm : SDNodeXForm<imm, [{
157  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
158}]>;
159
160def as_i32imm: SDNodeXForm<imm, [{
161  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
162}]>;
163
164def as_i64imm: SDNodeXForm<imm, [{
165  return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
166}]>;
167
168// Copied from the AArch64 backend:
169def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
170return CurDAG->getTargetConstant(
171  N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
172}]>;
173
174// Copied from the AArch64 backend:
175def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
176return CurDAG->getTargetConstant(
177  N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
178}]>;
179
180def IMM8bit : PatLeaf <(imm),
181  [{return isUInt<8>(N->getZExtValue());}]
182>;
183
184def IMM12bit : PatLeaf <(imm),
185  [{return isUInt<12>(N->getZExtValue());}]
186>;
187
188def IMM16bit : PatLeaf <(imm),
189  [{return isUInt<16>(N->getZExtValue());}]
190>;
191
192def IMM20bit : PatLeaf <(imm),
193  [{return isUInt<20>(N->getZExtValue());}]
194>;
195
196def IMM32bit : PatLeaf <(imm),
197  [{return isUInt<32>(N->getZExtValue());}]
198>;
199
200def mubuf_vaddr_offset : PatFrag<
201  (ops node:$ptr, node:$offset, node:$imm_offset),
202  (add (add node:$ptr, node:$offset), node:$imm_offset)
203>;
204
205class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
206  return isInlineImmediate(N);
207}]>;
208
209class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
210  return isInlineImmediate(N);
211}]>;
212
213class SGPRImm <dag frag> : PatLeaf<frag, [{
214  if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
215      AMDGPUSubtarget::SOUTHERN_ISLANDS) {
216    return false;
217  }
218  const SIRegisterInfo *SIRI =
219                       static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
220  for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
221                                                U != E; ++U) {
222    if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
223      return true;
224    }
225  }
226  return false;
227}]>;
228
229//===----------------------------------------------------------------------===//
230// Custom Operands
231//===----------------------------------------------------------------------===//
232
233def FRAMEri32 : Operand<iPTR> {
234  let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
235}
236
237def sopp_brtarget : Operand<OtherVT> {
238  let EncoderMethod = "getSOPPBrEncoding";
239  let OperandType = "OPERAND_PCREL";
240}
241
242include "SIInstrFormats.td"
243include "VIInstrFormats.td"
244
245let OperandType = "OPERAND_IMMEDIATE" in {
246
247def offen : Operand<i1> {
248  let PrintMethod = "printOffen";
249}
250def idxen : Operand<i1> {
251  let PrintMethod = "printIdxen";
252}
253def addr64 : Operand<i1> {
254  let PrintMethod = "printAddr64";
255}
256def mbuf_offset : Operand<i16> {
257  let PrintMethod = "printMBUFOffset";
258}
259def ds_offset : Operand<i16> {
260  let PrintMethod = "printDSOffset";
261}
262def ds_offset0 : Operand<i8> {
263  let PrintMethod = "printDSOffset0";
264}
265def ds_offset1 : Operand<i8> {
266  let PrintMethod = "printDSOffset1";
267}
268def glc : Operand <i1> {
269  let PrintMethod = "printGLC";
270}
271def slc : Operand <i1> {
272  let PrintMethod = "printSLC";
273}
274def tfe : Operand <i1> {
275  let PrintMethod = "printTFE";
276}
277
278def omod : Operand <i32> {
279  let PrintMethod = "printOModSI";
280}
281
282def ClampMod : Operand <i1> {
283  let PrintMethod = "printClampSI";
284}
285
286} // End OperandType = "OPERAND_IMMEDIATE"
287
288//===----------------------------------------------------------------------===//
289// Complex patterns
290//===----------------------------------------------------------------------===//
291
292def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
293def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
294
295def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
296def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
297def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
298def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
299def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
300def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
301
302def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
303def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
304def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
305def VOP3Mods  : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
306
307//===----------------------------------------------------------------------===//
308// SI assembler operands
309//===----------------------------------------------------------------------===//
310
311def SIOperand {
312  int ZERO = 0x80;
313  int VCC = 0x6A;
314  int FLAT_SCR = 0x68;
315}
316
317def SRCMODS {
318  int NONE = 0;
319}
320
321def DSTCLAMP {
322  int NONE = 0;
323}
324
325def DSTOMOD {
326  int NONE = 0;
327}
328
329//===----------------------------------------------------------------------===//
330//
331// SI Instruction multiclass helpers.
332//
333// Instructions with _32 take 32-bit operands.
334// Instructions with _64 take 64-bit operands.
335//
336// VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
337// encoding is the standard encoding, but instruction that make use of
338// any of the instruction modifiers must use the 64-bit encoding.
339//
340// Instructions with _e32 use the 32-bit encoding.
341// Instructions with _e64 use the 64-bit encoding.
342//
343//===----------------------------------------------------------------------===//
344
345class SIMCInstr <string pseudo, int subtarget> {
346  string PseudoInstr = pseudo;
347  int Subtarget = subtarget;
348}
349
350//===----------------------------------------------------------------------===//
351// EXP classes
352//===----------------------------------------------------------------------===//
353
354class EXPCommon : InstSI<
355  (outs),
356  (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
357       VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
358  "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
359  [] > {
360
361  let EXP_CNT = 1;
362  let Uses = [EXEC];
363}
364
365multiclass EXP_m {
366
367  let isPseudo = 1 in {
368    def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
369  }
370
371  def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
372
373  def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
374}
375
376//===----------------------------------------------------------------------===//
377// Scalar classes
378//===----------------------------------------------------------------------===//
379
380class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
381  SOP1 <outs, ins, "", pattern>,
382  SIMCInstr<opName, SISubtarget.NONE> {
383  let isPseudo = 1;
384}
385
386class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm,
387                    list<dag> pattern> :
388  SOP1 <outs, ins, asm, pattern>,
389  SOP1e <op.SI>,
390  SIMCInstr<opName, SISubtarget.SI>;
391
392class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm,
393                    list<dag> pattern> :
394  SOP1 <outs, ins, asm, pattern>,
395  SOP1e <op.VI>,
396  SIMCInstr<opName, SISubtarget.VI>;
397
398multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> {
399  def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
400    pattern>;
401
402  def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
403    opName#" $dst, $src0", pattern>;
404
405  def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
406    opName#" $dst, $src0", pattern>;
407}
408
409multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> {
410  def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
411    pattern>;
412
413  def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
414    opName#" $dst, $src0", pattern>;
415
416  def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
417    opName#" $dst, $src0", pattern>;
418}
419
420// no input, 64-bit output.
421multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
422  def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
423
424  def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
425    opName#" $dst", pattern> {
426    let SSRC0 = 0;
427  }
428
429  def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
430    opName#" $dst", pattern> {
431    let SSRC0 = 0;
432  }
433}
434
435// 64-bit input, 32-bit output.
436multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> {
437  def "" : SOP1_Pseudo <opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
438    pattern>;
439
440  def _si : SOP1_Real_si <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
441    opName#" $dst, $src0", pattern>;
442
443  def _vi : SOP1_Real_vi <op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
444    opName#" $dst, $src0", pattern>;
445}
446
447class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
448  SOP2<outs, ins, "", pattern>,
449  SIMCInstr<opName, SISubtarget.NONE> {
450  let isPseudo = 1;
451  let Size = 4;
452}
453
454class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm,
455                   list<dag> pattern> :
456  SOP2<outs, ins, asm, pattern>,
457  SOP2e<op.SI>,
458  SIMCInstr<opName, SISubtarget.SI>;
459
460class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm,
461                   list<dag> pattern> :
462  SOP2<outs, ins, asm, pattern>,
463  SOP2e<op.VI>,
464  SIMCInstr<opName, SISubtarget.VI>;
465
466multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
467  def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
468    (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
469
470  def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
471    (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
472    opName#" $dst, $src0, $src1 [$scc]", pattern>;
473
474  def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
475    (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
476    opName#" $dst, $src0, $src1 [$scc]", pattern>;
477}
478
479multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> {
480  def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
481    (ins SSrc_32:$src0, SSrc_32:$src1), pattern>;
482
483  def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
484    (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
485
486  def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
487    (ins SSrc_32:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
488}
489
490multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> {
491  def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
492    (ins SSrc_64:$src0, SSrc_64:$src1), pattern>;
493
494  def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
495    (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
496
497  def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
498    (ins SSrc_64:$src0, SSrc_64:$src1), opName#" $dst, $src0, $src1", pattern>;
499}
500
501multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> {
502  def "" : SOP2_Pseudo <opName, (outs SReg_64:$dst),
503    (ins SSrc_64:$src0, SSrc_32:$src1), pattern>;
504
505  def _si : SOP2_Real_si <op, opName, (outs SReg_64:$dst),
506    (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
507
508  def _vi : SOP2_Real_vi <op, opName, (outs SReg_64:$dst),
509    (ins SSrc_64:$src0, SSrc_32:$src1), opName#" $dst, $src0, $src1", pattern>;
510}
511
512
513class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
514                    string opName, PatLeaf cond> : SOPC <
515  op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
516  opName#" $dst, $src0, $src1", []>;
517
518class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
519  : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
520
521class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
522  : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
523
524class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
525  SOPK <outs, ins, "", pattern>,
526  SIMCInstr<opName, SISubtarget.NONE> {
527  let isPseudo = 1;
528}
529
530class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm,
531                    list<dag> pattern> :
532  SOPK <outs, ins, asm, pattern>,
533  SOPKe <op.SI>,
534  SIMCInstr<opName, SISubtarget.SI>;
535
536class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm,
537                    list<dag> pattern> :
538  SOPK <outs, ins, asm, pattern>,
539  SOPKe <op.VI>,
540  SIMCInstr<opName, SISubtarget.VI>;
541
542multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
543  def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
544    pattern>;
545
546  def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
547    opName#" $dst, $src0", pattern>;
548
549  def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
550    opName#" $dst, $src0", pattern>;
551}
552
553multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
554  def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
555    (ins SReg_32:$src0, u16imm:$src1), pattern>;
556
557  def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
558    (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
559
560  def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
561    (ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0", pattern>;
562}
563
564//===----------------------------------------------------------------------===//
565// SMRD classes
566//===----------------------------------------------------------------------===//
567
568class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
569  SMRD <outs, ins, "", pattern>,
570  SIMCInstr<opName, SISubtarget.NONE> {
571  let isPseudo = 1;
572}
573
574class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
575                    string asm> :
576  SMRD <outs, ins, asm, []>,
577  SMRDe <op, imm>,
578  SIMCInstr<opName, SISubtarget.SI>;
579
580class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
581                    string asm> :
582  SMRD <outs, ins, asm, []>,
583  SMEMe_vi <op, imm>,
584  SIMCInstr<opName, SISubtarget.VI>;
585
586multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
587                   string asm, list<dag> pattern> {
588
589  def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
590
591  def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
592
593  def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
594}
595
596multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
597                        RegisterClass dstClass> {
598  defm _IMM : SMRD_m <
599    op, opName#"_IMM", 1, (outs dstClass:$dst),
600    (ins baseClass:$sbase, u32imm:$offset),
601    opName#" $dst, $sbase, $offset", []
602  >;
603
604  defm _SGPR : SMRD_m <
605    op, opName#"_SGPR", 0, (outs dstClass:$dst),
606    (ins baseClass:$sbase, SReg_32:$soff),
607    opName#" $dst, $sbase, $soff", []
608  >;
609}
610
611//===----------------------------------------------------------------------===//
612// Vector ALU classes
613//===----------------------------------------------------------------------===//
614
615// This must always be right before the operand being input modified.
616def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
617  let PrintMethod = "printOperandAndMods";
618}
619def InputModsNoDefault : Operand <i32> {
620  let PrintMethod = "printOperandAndMods";
621}
622
623class getNumSrcArgs<ValueType Src1, ValueType Src2> {
624  int ret =
625    !if (!eq(Src1.Value, untyped.Value),      1,   // VOP1
626         !if (!eq(Src2.Value, untyped.Value), 2,   // VOP2
627                                              3)); // VOP3
628}
629
630// Returns the register class to use for the destination of VOP[123C]
631// instructions for the given VT.
632class getVALUDstForVT<ValueType VT> {
633  RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
634                          !if(!eq(VT.Size, 64), VReg_64,
635                            SReg_64)); // else VT == i1
636}
637
638// Returns the register class to use for source 0 of VOP[12C]
639// instructions for the given VT.
640class getVOPSrc0ForVT<ValueType VT> {
641  RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
642}
643
644// Returns the register class to use for source 1 of VOP[12C] for the
645// given VT.
646class getVOPSrc1ForVT<ValueType VT> {
647  RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
648}
649
650// Returns the register classes for the source arguments of a VOP[12C]
651// instruction for the given SrcVTs.
652class getInRC32 <list<ValueType> SrcVT> {
653  list<DAGOperand> ret = [
654    getVOPSrc0ForVT<SrcVT[0]>.ret,
655    getVOPSrc1ForVT<SrcVT[1]>.ret
656  ];
657}
658
659// Returns the register class to use for sources of VOP3 instructions for the
660// given VT.
661class getVOP3SrcForVT<ValueType VT> {
662  RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
663}
664
665// Returns the register classes for the source arguments of a VOP3
666// instruction for the given SrcVTs.
667class getInRC64 <list<ValueType> SrcVT> {
668  list<DAGOperand> ret = [
669    getVOP3SrcForVT<SrcVT[0]>.ret,
670    getVOP3SrcForVT<SrcVT[1]>.ret,
671    getVOP3SrcForVT<SrcVT[2]>.ret
672  ];
673}
674
675// Returns 1 if the source arguments have modifiers, 0 if they do not.
676class hasModifiers<ValueType SrcVT> {
677  bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
678            !if(!eq(SrcVT.Value, f64.Value), 1, 0));
679}
680
681// Returns the input arguments for VOP[12C] instructions for the given SrcVT.
682class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
683  dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0),               // VOP1
684            !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
685                                    (ins)));
686}
687
688// Returns the input arguments for VOP3 instructions for the given SrcVT.
689class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
690                RegisterOperand Src2RC, int NumSrcArgs,
691                bit HasModifiers> {
692
693  dag ret =
694    !if (!eq(NumSrcArgs, 1),
695      !if (!eq(HasModifiers, 1),
696        // VOP1 with modifiers
697        (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
698             ClampMod:$clamp, omod:$omod)
699      /* else */,
700        // VOP1 without modifiers
701        (ins Src0RC:$src0)
702      /* endif */ ),
703    !if (!eq(NumSrcArgs, 2),
704      !if (!eq(HasModifiers, 1),
705        // VOP 2 with modifiers
706        (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
707             InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
708             ClampMod:$clamp, omod:$omod)
709      /* else */,
710        // VOP2 without modifiers
711        (ins Src0RC:$src0, Src1RC:$src1)
712      /* endif */ )
713    /* NumSrcArgs == 3 */,
714      !if (!eq(HasModifiers, 1),
715        // VOP3 with modifiers
716        (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
717             InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
718             InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
719             ClampMod:$clamp, omod:$omod)
720      /* else */,
721        // VOP3 without modifiers
722        (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
723      /* endif */ )));
724}
725
726// Returns the assembly string for the inputs and outputs of a VOP[12C]
727// instruction.  This does not add the _e32 suffix, so it can be reused
728// by getAsm64.
729class getAsm32 <int NumSrcArgs> {
730  string src1 = ", $src1";
731  string src2 = ", $src2";
732  string ret = " $dst, $src0"#
733               !if(!eq(NumSrcArgs, 1), "", src1)#
734               !if(!eq(NumSrcArgs, 3), src2, "");
735}
736
737// Returns the assembly string for the inputs and outputs of a VOP3
738// instruction.
739class getAsm64 <int NumSrcArgs, bit HasModifiers> {
740  string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
741  string src1 = !if(!eq(NumSrcArgs, 1), "",
742                   !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
743                                           " $src1_modifiers,"));
744  string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
745  string ret =
746  !if(!eq(HasModifiers, 0),
747      getAsm32<NumSrcArgs>.ret,
748      " $dst, "#src0#src1#src2#"$clamp"#"$omod");
749}
750
751
752class VOPProfile <list<ValueType> _ArgVT> {
753
754  field list<ValueType> ArgVT = _ArgVT;
755
756  field ValueType DstVT = ArgVT[0];
757  field ValueType Src0VT = ArgVT[1];
758  field ValueType Src1VT = ArgVT[2];
759  field ValueType Src2VT = ArgVT[3];
760  field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
761  field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
762  field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
763  field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
764  field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
765  field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
766
767  field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
768  field bit HasModifiers = hasModifiers<Src0VT>.ret;
769
770  field dag Outs = (outs DstRC:$dst);
771
772  field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
773  field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
774                             HasModifiers>.ret;
775
776  field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
777  field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
778}
779
780def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
781def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
782def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
783def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
784def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
785def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
786def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
787def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
788def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
789
790def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
791def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
792def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
793def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
794def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
795def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
796def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
797  let Src0RC32 = VCSrc_32;
798}
799
800def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
801  let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
802  let Asm64 = " $dst, $src0_modifiers, $src1";
803}
804
805def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
806  let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
807  let Asm64 = " $dst, $src0_modifiers, $src1";
808}
809
810def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
811def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
812
813def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
814def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
815def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
816def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
817
818
819class VOP <string opName> {
820  string OpName = opName;
821}
822
823class VOP2_REV <string revOp, bit isOrig> {
824  string RevOp = revOp;
825  bit IsOrig = isOrig;
826}
827
828class AtomicNoRet <string noRetOp, bit isRet> {
829  string NoRetOp = noRetOp;
830  bit IsRet = isRet;
831}
832
833class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
834  VOP1Common <outs, ins, "", pattern>,
835  VOP <opName>,
836  SIMCInstr <opName#"_e32", SISubtarget.NONE> {
837  let isPseudo = 1;
838}
839
840multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
841                   string opName> {
842  def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
843
844  def _si : VOP1<op.SI, outs, ins, asm, []>,
845            SIMCInstr <opName#"_e32", SISubtarget.SI>;
846  def _vi : VOP1<op.VI, outs, ins, asm, []>,
847            SIMCInstr <opName#"_e32", SISubtarget.VI>;
848}
849
850class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
851  VOP2Common <outs, ins, "", pattern>,
852  VOP <opName>,
853  SIMCInstr<opName#"_e32", SISubtarget.NONE> {
854  let isPseudo = 1;
855}
856
857multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
858                     string opName, string revOpSI> {
859  def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
860           VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
861
862  def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
863            VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
864            SIMCInstr <opName#"_e32", SISubtarget.SI>;
865}
866
867multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
868                   string opName, string revOpSI, string revOpVI> {
869  def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
870           VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
871
872  def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
873            VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
874            SIMCInstr <opName#"_e32", SISubtarget.SI>;
875  def _vi : VOP2 <op.VI, outs, ins, opName#asm, []>,
876            VOP2_REV<revOpVI#"_e32_vi", !eq(revOpVI, opName)>,
877            SIMCInstr <opName#"_e32", SISubtarget.VI>;
878}
879
880class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
881
882  bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
883  bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
884  bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
885  bits<2> omod = !if(HasModifiers, ?, 0);
886  bits<1> clamp = !if(HasModifiers, ?, 0);
887  bits<9> src1 = !if(HasSrc1, ?, 0);
888  bits<9> src2 = !if(HasSrc2, ?, 0);
889}
890
891class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
892  VOP3Common <outs, ins, "", pattern>,
893  VOP <opName>,
894  SIMCInstr<opName#"_e64", SISubtarget.NONE> {
895  let isPseudo = 1;
896}
897
898class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
899  VOP3Common <outs, ins, asm, []>,
900  VOP3e <op>,
901  SIMCInstr<opName#"_e64", SISubtarget.SI>;
902
903class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
904  VOP3Common <outs, ins, asm, []>,
905  VOP3e_vi <op>,
906  SIMCInstr <opName#"_e64", SISubtarget.VI>;
907
908multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
909                   string opName, int NumSrcArgs, bit HasMods = 1> {
910
911  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
912
913  def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
914            VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
915                              !if(!eq(NumSrcArgs, 2), 0, 1),
916                              HasMods>;
917  def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
918            VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
919                              !if(!eq(NumSrcArgs, 2), 0, 1),
920                              HasMods>;
921}
922
923// VOP3_m without source modifiers
924multiclass VOP3_m_nosrcmod <vop op, dag outs, dag ins, string asm, list<dag> pattern,
925                   string opName, int NumSrcArgs, bit HasMods = 1> {
926
927  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
928
929  let src0_modifiers = 0,
930      src1_modifiers = 0,
931      src2_modifiers = 0 in {
932    def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
933    def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
934  }
935}
936
937multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
938                     list<dag> pattern, string opName, bit HasMods = 1> {
939
940  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
941
942  def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
943            VOP3DisableFields<0, 0, HasMods>;
944
945  def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
946            VOP3DisableFields<0, 0, HasMods>;
947}
948
949multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
950                     list<dag> pattern, string opName, string revOpSI, string revOpVI,
951                     bit HasMods = 1, bit UseFullOp = 0> {
952
953  def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
954           VOP2_REV<revOpSI#"_e64", !eq(revOpSI, opName)>;
955
956  def _si : VOP3_Real_si <op.SI3,
957              outs, ins, asm, opName>,
958            VOP2_REV<revOpSI#"_e64_si", !eq(revOpSI, opName)>,
959            VOP3DisableFields<1, 0, HasMods>;
960
961  def _vi : VOP3_Real_vi <op.VI3,
962              outs, ins, asm, opName>,
963            VOP2_REV<revOpVI#"_e64_vi", !eq(revOpVI, opName)>,
964            VOP3DisableFields<1, 0, HasMods>;
965}
966
967multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
968                      list<dag> pattern, string opName, string revOp,
969                      bit HasMods = 1, bit UseFullOp = 0> {
970  def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
971           VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
972
973  // The VOP2 variant puts the carry out into VCC, the VOP3 variant
974  // can write it into any SGPR. We currently don't use the carry out,
975  // so for now hardcode it to VCC as well.
976  let sdst = SIOperand.VCC, Defs = [VCC] in {
977    def _si : VOP3b <op.SI3, outs, ins, asm, pattern>,
978              VOP3DisableFields<1, 0, HasMods>,
979              SIMCInstr<opName#"_e64", SISubtarget.SI>,
980              VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
981
982    // TODO: Do we need this VI variant here?
983    /*def _vi : VOP3b_vi <op.VI3, outs, ins, asm, pattern>,
984              VOP3DisableFields<1, 0, HasMods>,
985              SIMCInstr<opName#"_e64", SISubtarget.VI>,
986              VOP2_REV<revOp#"_e64_vi", !eq(revOp, opName)>;*/
987  } // End sdst = SIOperand.VCC, Defs = [VCC]
988}
989
990multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
991                     list<dag> pattern, string opName,
992                     bit HasMods, bit defExec> {
993
994  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
995
996  def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
997            VOP3DisableFields<1, 0, HasMods> {
998    let Defs = !if(defExec, [EXEC], []);
999  }
1000
1001  def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1002            VOP3DisableFields<1, 0, HasMods> {
1003    let Defs = !if(defExec, [EXEC], []);
1004  }
1005}
1006
1007// An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1008multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1009                         string asm, list<dag> pattern = []> {
1010  let isPseudo = 1 in {
1011    def "" : VOPAnyCommon <outs, ins, "", pattern>,
1012             SIMCInstr<opName, SISubtarget.NONE>;
1013  }
1014
1015  def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1016            SIMCInstr <opName, SISubtarget.SI>;
1017
1018  def _vi : VOP3Common <outs, ins, asm, []>,
1019            VOP3e_vi <op.VI3>,
1020            VOP3DisableFields <1, 0, 0>,
1021            SIMCInstr <opName, SISubtarget.VI>;
1022}
1023
1024multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1025                        dag ins32, string asm32, list<dag> pat32,
1026                        dag ins64, string asm64, list<dag> pat64,
1027                        bit HasMods> {
1028
1029  defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1030
1031  defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
1032}
1033
1034multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1035                     SDPatternOperator node = null_frag> : VOP1_Helper <
1036  op, opName, P.Outs,
1037  P.Ins32, P.Asm32, [],
1038  P.Ins64, P.Asm64,
1039  !if(P.HasModifiers,
1040      [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1041                                i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1042      [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1043  P.HasModifiers
1044>;
1045
1046multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1047                       SDPatternOperator node = null_frag> {
1048
1049  def _e32 : VOP1 <op.SI, P.Outs, P.Ins32, opName#P.Asm32, []>,
1050             VOP <opName>;
1051
1052  def _e64 : VOP3Common <P.Outs, P.Ins64, opName#P.Asm64,
1053    !if(P.HasModifiers,
1054      [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1055                                i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1056      [(set P.DstVT:$dst, (node P.Src0VT:$src0))])>,
1057            VOP <opName>,
1058            VOP3e <op.SI3>,
1059            VOP3DisableFields<0, 0, P.HasModifiers>;
1060}
1061
1062multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1063                        dag ins32, string asm32, list<dag> pat32,
1064                        dag ins64, string asm64, list<dag> pat64,
1065                        string revOpSI, string revOpVI, bit HasMods> {
1066  defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOpSI, revOpVI>;
1067
1068  defm _e64 : VOP3_2_m <op,
1069    outs, ins64, opName#"_e64"#asm64, pat64, opName, revOpSI, revOpVI, HasMods
1070  >;
1071}
1072
1073multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1074                     SDPatternOperator node = null_frag,
1075                     string revOpSI = opName, string revOpVI = revOpSI> : VOP2_Helper <
1076  op, opName, P.Outs,
1077  P.Ins32, P.Asm32, [],
1078  P.Ins64, P.Asm64,
1079  !if(P.HasModifiers,
1080      [(set P.DstVT:$dst,
1081           (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1082                                      i1:$clamp, i32:$omod)),
1083                 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1084      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1085  revOpSI, revOpVI, P.HasModifiers
1086>;
1087
1088multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1089                         dag ins32, string asm32, list<dag> pat32,
1090                         dag ins64, string asm64, list<dag> pat64,
1091                         string revOp, bit HasMods> {
1092
1093  defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp, revOp>;
1094
1095  defm _e64 : VOP3b_2_m <op,
1096    outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
1097  >;
1098}
1099
1100multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1101                      SDPatternOperator node = null_frag,
1102                      string revOp = opName> : VOP2b_Helper <
1103  op, opName, P.Outs,
1104  P.Ins32, P.Asm32, [],
1105  P.Ins64, P.Asm64,
1106  !if(P.HasModifiers,
1107      [(set P.DstVT:$dst,
1108           (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1109                                      i1:$clamp, i32:$omod)),
1110                 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1111      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1112  revOp, P.HasModifiers
1113>;
1114
1115// A VOP2 instruction that is VOP3-only on VI.
1116multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1117                            dag ins32, string asm32, list<dag> pat32,
1118                            dag ins64, string asm64, list<dag> pat64,
1119                            string revOpSI, string revOpVI, bit HasMods> {
1120  defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
1121
1122  defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
1123                        revOpSI, revOpVI, HasMods>;
1124}
1125
1126multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1127                          SDPatternOperator node = null_frag,
1128                          string revOpSI = opName, string revOpVI = revOpSI>
1129                          : VOP2_VI3_Helper <
1130  op, opName, P.Outs,
1131  P.Ins32, P.Asm32, [],
1132  P.Ins64, P.Asm64,
1133  !if(P.HasModifiers,
1134      [(set P.DstVT:$dst,
1135           (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1136                                      i1:$clamp, i32:$omod)),
1137                 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1138      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1139  revOpSI, revOpVI, P.HasModifiers
1140>;
1141
1142class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1143  VOPCCommon <ins, "", pattern>,
1144  VOP <opName>,
1145  SIMCInstr<opName#"_e32", SISubtarget.NONE> {
1146  let isPseudo = 1;
1147}
1148
1149multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1150                   string opName, bit DefExec> {
1151  def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1152
1153  def _si : VOPC<op.SI, ins, asm, []>,
1154            SIMCInstr <opName#"_e32", SISubtarget.SI> {
1155    let Defs = !if(DefExec, [EXEC], []);
1156  }
1157
1158  def _vi : VOPC<op.VI, ins, asm, []>,
1159            SIMCInstr <opName#"_e32", SISubtarget.VI> {
1160    let Defs = !if(DefExec, [EXEC], []);
1161  }
1162}
1163
1164multiclass VOPC_Helper <vopc op, string opName,
1165                        dag ins32, string asm32, list<dag> pat32,
1166                        dag out64, dag ins64, string asm64, list<dag> pat64,
1167                        bit HasMods, bit DefExec> {
1168  defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1169
1170  defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
1171                        opName, HasMods, DefExec>;
1172}
1173
1174multiclass VOPCInst <vopc op, string opName,
1175                     VOPProfile P, PatLeaf cond = COND_NULL,
1176                     bit DefExec = 0> : VOPC_Helper <
1177  op, opName,
1178  P.Ins32, P.Asm32, [],
1179  (outs SReg_64:$dst), P.Ins64, P.Asm64,
1180  !if(P.HasModifiers,
1181      [(set i1:$dst,
1182          (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1183                                      i1:$clamp, i32:$omod)),
1184                 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1185                 cond))],
1186      [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1187  P.HasModifiers, DefExec
1188>;
1189
1190multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1191                     bit DefExec = 0> : VOPC_Helper <
1192  op, opName,
1193  P.Ins32, P.Asm32, [],
1194  (outs SReg_64:$dst), P.Ins64, P.Asm64,
1195  !if(P.HasModifiers,
1196      [(set i1:$dst,
1197          (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1198      [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1199  P.HasModifiers, DefExec
1200>;
1201
1202
1203multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1204  VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
1205
1206multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1207  VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
1208
1209multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1210  VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
1211
1212multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1213  VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
1214
1215
1216multiclass VOPCX <vopc op, string opName, VOPProfile P,
1217                  PatLeaf cond = COND_NULL>
1218  : VOPCInst <op, opName, P, cond, 1>;
1219
1220multiclass VOPCX_F32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1221  VOPCX <op, opName, VOP_F32_F32_F32, cond>;
1222
1223multiclass VOPCX_F64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1224  VOPCX <op, opName, VOP_F64_F64_F64, cond>;
1225
1226multiclass VOPCX_I32 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1227  VOPCX <op, opName, VOP_I32_I32_I32, cond>;
1228
1229multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
1230  VOPCX <op, opName, VOP_I64_I64_I64, cond>;
1231
1232multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1233                        list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1234    op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
1235>;
1236
1237multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1238  VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1239
1240multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1241  VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1242
1243multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1244  VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1245
1246multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1247  VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1248
1249multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1250                     SDPatternOperator node = null_frag> : VOP3_Helper <
1251  op, opName, P.Outs, P.Ins64, P.Asm64,
1252  !if(!eq(P.NumSrcArgs, 3),
1253    !if(P.HasModifiers,
1254        [(set P.DstVT:$dst,
1255            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1256                                       i1:$clamp, i32:$omod)),
1257                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1258                  (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1259        [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1260                                  P.Src2VT:$src2))]),
1261  !if(!eq(P.NumSrcArgs, 2),
1262    !if(P.HasModifiers,
1263        [(set P.DstVT:$dst,
1264            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1265                                       i1:$clamp, i32:$omod)),
1266                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1267        [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1268  /* P.NumSrcArgs == 1 */,
1269    !if(P.HasModifiers,
1270        [(set P.DstVT:$dst,
1271            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1272                                       i1:$clamp, i32:$omod))))],
1273        [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1274  P.NumSrcArgs, P.HasModifiers
1275>;
1276
1277multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1278                    string opName, list<dag> pattern> :
1279  VOP3b_2_m <
1280  op, (outs vrc:$vdst, SReg_64:$sdst),
1281      (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1282           InputModsNoDefault:$src1_modifiers, arc:$src1,
1283           InputModsNoDefault:$src2_modifiers, arc:$src2,
1284           ClampMod:$clamp, omod:$omod),
1285  opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1286  opName, opName, 1, 1
1287>;
1288
1289multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1290  VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1291
1292multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1293  VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1294
1295
1296class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1297  (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1298        (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1299        (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1300  (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1301        i32:$src1_modifiers, P.Src1VT:$src1,
1302        i32:$src2_modifiers, P.Src2VT:$src2,
1303        i1:$clamp,
1304        i32:$omod)>;
1305
1306//===----------------------------------------------------------------------===//
1307// Interpolation opcodes
1308//===----------------------------------------------------------------------===//
1309
1310class VINTRP_Pseudo <string opName, dag outs, dag ins, string asm,
1311                     list<dag> pattern> :
1312  VINTRPCommon <outs, ins, asm, pattern>,
1313  SIMCInstr<opName, SISubtarget.NONE> {
1314  let isPseudo = 1;
1315}
1316
1317class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1318                      string asm, list<dag> pattern> :
1319  VINTRPCommon <outs, ins, asm, pattern>,
1320  VINTRPe <op>,
1321  SIMCInstr<opName, SISubtarget.SI>;
1322
1323class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1324                      string asm, list<dag> pattern> :
1325  VINTRPCommon <outs, ins, asm, pattern>,
1326  VINTRPe_vi <op>,
1327  SIMCInstr<opName, SISubtarget.VI>;
1328
1329multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1330                     string disableEncoding = "", string constraints = "",
1331                     list<dag> pattern = []> {
1332  let DisableEncoding = disableEncoding,
1333      Constraints = constraints in {
1334    def "" : VINTRP_Pseudo <opName, outs, ins, asm, pattern>;
1335
1336    def _si : VINTRP_Real_si <op, opName, outs, ins, asm, pattern>;
1337
1338    def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm, pattern>;
1339  }
1340}
1341
1342//===----------------------------------------------------------------------===//
1343// Vector I/O classes
1344//===----------------------------------------------------------------------===//
1345
1346class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1347  DS <outs, ins, "", pattern>,
1348  SIMCInstr <opName, SISubtarget.NONE> {
1349  let isPseudo = 1;
1350}
1351
1352class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1353  DS <outs, ins, asm, []>,
1354  DSe <op>,
1355  SIMCInstr <opName, SISubtarget.SI>;
1356
1357class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1358  DS <outs, ins, asm, []>,
1359  DSe_vi <op>,
1360  SIMCInstr <opName, SISubtarget.VI>;
1361
1362class DS_1A_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1363  DS <outs, ins, asm, []>,
1364  DSe <op>,
1365  SIMCInstr <opName, SISubtarget.SI> {
1366
1367  // Single load interpret the 2 i8imm operands as a single i16 offset.
1368  bits<16> offset;
1369  let offset0 = offset{7-0};
1370  let offset1 = offset{15-8};
1371}
1372
1373class DS_1A_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1374  DS <outs, ins, asm, []>,
1375  DSe_vi <op>,
1376  SIMCInstr <opName, SISubtarget.VI> {
1377
1378  // Single load interpret the 2 i8imm operands as a single i16 offset.
1379  bits<16> offset;
1380  let offset0 = offset{7-0};
1381  let offset1 = offset{15-8};
1382}
1383
1384multiclass DS_1A_Load_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1385                         list<dag> pat> {
1386  let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1387    def "" : DS_Pseudo <opName, outs, ins, pat>;
1388
1389    let data0 = 0, data1 = 0 in {
1390      def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1391      def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1392    }
1393  }
1394}
1395
1396multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
1397    : DS_1A_Load_m <
1398  op,
1399  asm,
1400  (outs regClass:$vdst),
1401  (ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
1402  asm#" $vdst, $addr"#"$offset"#" [M0]",
1403  []>;
1404
1405multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
1406                       list<dag> pat> {
1407  let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
1408    def "" : DS_Pseudo <opName, outs, ins, pat>;
1409
1410    let data0 = 0, data1 = 0 in {
1411      def _si : DS_Real_si <op, opName, outs, ins, asm>;
1412      def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1413    }
1414  }
1415}
1416
1417multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
1418    : DS_Load2_m <
1419  op,
1420  asm,
1421  (outs regClass:$vdst),
1422  (ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1423        M0Reg:$m0),
1424  asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
1425  []>;
1426
1427multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
1428                          string asm, list<dag> pat> {
1429  let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1430    def "" : DS_Pseudo <opName, outs, ins, pat>;
1431
1432    let data1 = 0, vdst = 0 in {
1433      def _si : DS_1A_Real_si <op, opName, outs, ins, asm>;
1434      def _vi : DS_1A_Real_vi <op, opName, outs, ins, asm>;
1435    }
1436  }
1437}
1438
1439multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
1440    : DS_1A_Store_m <
1441  op,
1442  asm,
1443  (outs),
1444  (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
1445  asm#" $addr, $data0"#"$offset"#" [M0]",
1446  []>;
1447
1448multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
1449                       string asm, list<dag> pat> {
1450  let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
1451    def "" : DS_Pseudo <opName, outs, ins, pat>;
1452
1453    let vdst = 0 in {
1454      def _si : DS_Real_si <op, opName, outs, ins, asm>;
1455      def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1456    }
1457  }
1458}
1459
1460multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
1461    : DS_Store_m <
1462  op,
1463  asm,
1464  (outs),
1465  (ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
1466       ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
1467  asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
1468  []>;
1469
1470class DS_1A_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
1471    DS_si <op, outs, ins, asm, pat> {
1472  bits<16> offset;
1473
1474  // Single load interpret the 2 i8imm operands as a single i16 offset.
1475  let offset0 = offset{7-0};
1476  let offset1 = offset{15-8};
1477
1478  let hasSideEffects = 0;
1479}
1480
1481// 1 address, 1 data.
1482class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1483  op,
1484  (outs rc:$vdst),
1485  (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1486  asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,
1487  AtomicNoRet<noRetOp, 1> {
1488
1489  let data1 = 0;
1490  let mayStore = 1;
1491  let mayLoad = 1;
1492
1493  let hasPostISelHook = 1; // Adjusted to no return version.
1494}
1495
1496// 1 address, 2 data.
1497class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A_si <
1498  op,
1499  (outs rc:$vdst),
1500  (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1501  asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
1502  []>,
1503  AtomicNoRet<noRetOp, 1> {
1504  let mayStore = 1;
1505  let mayLoad = 1;
1506  let hasPostISelHook = 1; // Adjusted to no return version.
1507}
1508
1509// 1 address, 2 data.
1510class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1511  op,
1512  (outs),
1513  (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
1514  asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
1515  []>,
1516  AtomicNoRet<noRetOp, 0> {
1517  let mayStore = 1;
1518  let mayLoad = 1;
1519}
1520
1521// 1 address, 1 data.
1522class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A_si <
1523  op,
1524  (outs),
1525  (ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
1526  asm#" $addr, $data0"#"$offset"#" [M0]",
1527  []>,
1528  AtomicNoRet<noRetOp, 0> {
1529
1530  let data1 = 0;
1531  let mayStore = 1;
1532  let mayLoad = 1;
1533}
1534
1535//===----------------------------------------------------------------------===//
1536// MTBUF classes
1537//===----------------------------------------------------------------------===//
1538
1539class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1540  MTBUF <outs, ins, "", pattern>,
1541  SIMCInstr<opName, SISubtarget.NONE> {
1542  let isPseudo = 1;
1543}
1544
1545class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1546                    string asm> :
1547  MTBUF <outs, ins, asm, []>,
1548  MTBUFe <op>,
1549  SIMCInstr<opName, SISubtarget.SI>;
1550
1551class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1552  MTBUF <outs, ins, asm, []>,
1553  MTBUFe_vi <op>,
1554  SIMCInstr <opName, SISubtarget.VI>;
1555
1556multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1557                    list<dag> pattern> {
1558
1559  def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1560
1561  def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1562
1563  def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1564
1565}
1566
1567let mayStore = 1, mayLoad = 0 in {
1568
1569multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1570                               RegisterClass regClass> : MTBUF_m <
1571  op, opName, (outs),
1572  (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1573   i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1574   SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1575  opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1576        #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1577>;
1578
1579} // mayStore = 1, mayLoad = 0
1580
1581let mayLoad = 1, mayStore = 0 in {
1582
1583multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1584                              RegisterClass regClass> : MTBUF_m <
1585  op, opName, (outs regClass:$dst),
1586  (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1587       i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1588       i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1589  opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1590        #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1591>;
1592
1593} // mayLoad = 1, mayStore = 0
1594
1595//===----------------------------------------------------------------------===//
1596// MUBUF classes
1597//===----------------------------------------------------------------------===//
1598
1599class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1600  MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1601  let lds  = 0;
1602}
1603
1604class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1605  MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1606  let lds = 0;
1607}
1608
1609class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1610
1611  bit IsAddr64 = is_addr64;
1612  string OpName = NAME # suffix;
1613}
1614
1615class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1616    : MUBUF_si <op, outs, ins, asm, pattern> {
1617
1618  let offen = 0;
1619  let idxen = 0;
1620  let addr64 = 1;
1621  let tfe = 0;
1622  let lds = 0;
1623  let soffset = 128;
1624}
1625
1626class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1627    : MUBUF_si <op, outs, ins, asm, pattern> {
1628
1629  let offen = 0;
1630  let idxen = 0;
1631  let addr64 = 0;
1632  let tfe = 0;
1633  let lds = 0;
1634  let vaddr = 0;
1635}
1636
1637multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1638                         ValueType vt, SDPatternOperator atomic> {
1639
1640  let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1641
1642    // No return variants
1643    let glc = 0 in {
1644
1645      def _ADDR64 : MUBUFAtomicAddr64 <
1646        op, (outs),
1647        (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1648             mbuf_offset:$offset, slc:$slc),
1649        name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1650      >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1651
1652      def _OFFSET : MUBUFAtomicOffset <
1653        op, (outs),
1654        (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1655             SCSrc_32:$soffset, slc:$slc),
1656        name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1657      >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1658    } // glc = 0
1659
1660    // Variant that return values
1661    let glc = 1, Constraints = "$vdata = $vdata_in",
1662        DisableEncoding = "$vdata_in"  in {
1663
1664      def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1665        op, (outs rc:$vdata),
1666        (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1667             mbuf_offset:$offset, slc:$slc),
1668        name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1669        [(set vt:$vdata,
1670         (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1671                                    i1:$slc), vt:$vdata_in))]
1672      >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1673
1674      def _RTN_OFFSET : MUBUFAtomicOffset <
1675        op, (outs rc:$vdata),
1676        (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1677             SCSrc_32:$soffset, slc:$slc),
1678        name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1679        [(set vt:$vdata,
1680         (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1681                                    i1:$slc), vt:$vdata_in))]
1682      >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1683
1684    } // glc = 1
1685
1686  } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1687}
1688
1689multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1690                              ValueType load_vt = i32,
1691                              SDPatternOperator ld = null_frag> {
1692
1693  let mayLoad = 1, mayStore = 0 in {
1694
1695    let addr64 = 0 in {
1696
1697      let offen = 0, idxen = 0, vaddr = 0 in {
1698        def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
1699                             (ins SReg_128:$srsrc,
1700                             mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1701                             slc:$slc, tfe:$tfe),
1702                             asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1703                             [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1704                                                       i32:$soffset, i16:$offset,
1705                                                       i1:$glc, i1:$slc, i1:$tfe)))]>,
1706                     MUBUFAddr64Table<0>;
1707      }
1708
1709      let offen = 1, idxen = 0  in {
1710        def _OFFEN  : MUBUF_si <op, (outs regClass:$vdata),
1711                             (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1712                             SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1713                             tfe:$tfe),
1714                             asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1715      }
1716
1717      let offen = 0, idxen = 1 in {
1718        def _IDXEN  : MUBUF_si <op, (outs regClass:$vdata),
1719                             (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1720                             mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1721                             slc:$slc, tfe:$tfe),
1722                             asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1723      }
1724
1725      let offen = 1, idxen = 1 in {
1726        def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
1727                             (ins SReg_128:$srsrc, VReg_64:$vaddr,
1728                             SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1729                             asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1730      }
1731    }
1732
1733    let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1734      def _ADDR64 : MUBUF_si <op, (outs regClass:$vdata),
1735                           (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1736                           asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1737                           [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1738                                                  i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1739    }
1740  }
1741}
1742
1743multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
1744                              ValueType load_vt = i32,
1745                              SDPatternOperator ld = null_frag> {
1746
1747  let lds = 0, mayLoad = 1 in {
1748    let offen = 0, idxen = 0, vaddr = 0 in {
1749      def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
1750                           (ins SReg_128:$srsrc,
1751                           mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1752                           slc:$slc, tfe:$tfe),
1753                           asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1754                           [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1755                                                     i32:$soffset, i16:$offset,
1756                                                     i1:$glc, i1:$slc, i1:$tfe)))]>,
1757                           MUBUFAddr64Table<0>;
1758    }
1759
1760    let offen = 1, idxen = 0  in {
1761      def _OFFEN  : MUBUF_vi <op, (outs regClass:$vdata),
1762                           (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1763                           SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1764                           tfe:$tfe),
1765                           asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1766    }
1767
1768    let offen = 0, idxen = 1 in {
1769      def _IDXEN  : MUBUF_vi <op, (outs regClass:$vdata),
1770                           (ins SReg_128:$srsrc, VGPR_32:$vaddr,
1771                           mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
1772                           slc:$slc, tfe:$tfe),
1773                           asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1774    }
1775
1776    let offen = 1, idxen = 1 in {
1777      def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
1778                           (ins SReg_128:$srsrc, VReg_64:$vaddr,
1779                           SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1780                           asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1781    }
1782  }
1783}
1784
1785multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1786                          ValueType store_vt, SDPatternOperator st> {
1787
1788  let mayLoad = 0, mayStore = 1 in {
1789  let addr64 = 0 in {
1790
1791    def "" : MUBUF_si <
1792      op, (outs),
1793      (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1794           mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1795           tfe:$tfe),
1796      name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1797           "$glc"#"$slc"#"$tfe",
1798      []
1799    >;
1800
1801    let offen = 0, idxen = 0, vaddr = 0 in {
1802      def _OFFSET : MUBUF_si <
1803        op, (outs),
1804        (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1805              SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1806        name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1807        [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1808                                           i16:$offset, i1:$glc, i1:$slc,
1809                                           i1:$tfe))]
1810      >, MUBUFAddr64Table<0>;
1811    } // offen = 0, idxen = 0, vaddr = 0
1812
1813    let offen = 1, idxen = 0  in {
1814      def _OFFEN  : MUBUF_si <
1815        op, (outs),
1816        (ins vdataClass:$vdata, SReg_128:$srsrc, VGPR_32:$vaddr, SCSrc_32:$soffset,
1817             mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1818        name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1819            "$glc"#"$slc"#"$tfe",
1820        []
1821      >;
1822    } // end offen = 1, idxen = 0
1823
1824  } // End addr64 = 0
1825
1826  def _ADDR64 : MUBUF_si <
1827    op, (outs),
1828    (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1829    name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1830    [(st store_vt:$vdata,
1831     (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1832     {
1833
1834      let mayLoad = 0;
1835      let mayStore = 1;
1836
1837      // Encoding
1838      let offen = 0;
1839      let idxen = 0;
1840      let glc = 0;
1841      let addr64 = 1;
1842      let slc = 0;
1843      let tfe = 0;
1844      let soffset = 128; // ZERO
1845   }
1846   } // End mayLoad = 0, mayStore = 1
1847}
1848
1849class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1850      FLAT <op, (outs regClass:$data),
1851                (ins VReg_64:$addr),
1852            asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1853  let glc = 0;
1854  let slc = 0;
1855  let tfe = 0;
1856  let mayLoad = 1;
1857}
1858
1859class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1860      FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1861          name#" $data, $addr, [M0, FLAT_SCRATCH]",
1862         []> {
1863
1864  let mayLoad = 0;
1865  let mayStore = 1;
1866
1867  // Encoding
1868  let glc = 0;
1869  let slc = 0;
1870  let tfe = 0;
1871}
1872
1873class MIMG_Mask <string op, int channels> {
1874  string Op = op;
1875  int Channels = channels;
1876}
1877
1878class MIMG_NoSampler_Helper <bits<7> op, string asm,
1879                             RegisterClass dst_rc,
1880                             RegisterClass src_rc> : MIMG <
1881  op,
1882  (outs dst_rc:$vdata),
1883  (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1884       i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1885       SReg_256:$srsrc),
1886  asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1887     #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1888  []> {
1889  let SSAMP = 0;
1890  let mayLoad = 1;
1891  let mayStore = 0;
1892  let hasPostISelHook = 1;
1893}
1894
1895multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1896                                      RegisterClass dst_rc,
1897                                      int channels> {
1898  def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
1899            MIMG_Mask<asm#"_V1", channels>;
1900  def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1901            MIMG_Mask<asm#"_V2", channels>;
1902  def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1903            MIMG_Mask<asm#"_V4", channels>;
1904}
1905
1906multiclass MIMG_NoSampler <bits<7> op, string asm> {
1907  defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
1908  defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1909  defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1910  defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1911}
1912
1913class MIMG_Sampler_Helper <bits<7> op, string asm,
1914                           RegisterClass dst_rc,
1915                           RegisterClass src_rc> : MIMG <
1916  op,
1917  (outs dst_rc:$vdata),
1918  (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1919       i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1920       SReg_256:$srsrc, SReg_128:$ssamp),
1921  asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1922     #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1923  []> {
1924  let mayLoad = 1;
1925  let mayStore = 0;
1926  let hasPostISelHook = 1;
1927}
1928
1929multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1930                                    RegisterClass dst_rc,
1931                                    int channels> {
1932  def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32>,
1933            MIMG_Mask<asm#"_V1", channels>;
1934  def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1935            MIMG_Mask<asm#"_V2", channels>;
1936  def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1937            MIMG_Mask<asm#"_V4", channels>;
1938  def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1939            MIMG_Mask<asm#"_V8", channels>;
1940  def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1941            MIMG_Mask<asm#"_V16", channels>;
1942}
1943
1944multiclass MIMG_Sampler <bits<7> op, string asm> {
1945  defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1>;
1946  defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1947  defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1948  defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1949}
1950
1951class MIMG_Gather_Helper <bits<7> op, string asm,
1952                          RegisterClass dst_rc,
1953                          RegisterClass src_rc> : MIMG <
1954  op,
1955  (outs dst_rc:$vdata),
1956  (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1957       i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1958       SReg_256:$srsrc, SReg_128:$ssamp),
1959  asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1960     #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1961  []> {
1962  let mayLoad = 1;
1963  let mayStore = 0;
1964
1965  // DMASK was repurposed for GATHER4. 4 components are always
1966  // returned and DMASK works like a swizzle - it selects
1967  // the component to fetch. The only useful DMASK values are
1968  // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1969  // (red,red,red,red) etc.) The ISA document doesn't mention
1970  // this.
1971  // Therefore, disable all code which updates DMASK by setting these two:
1972  let MIMG = 0;
1973  let hasPostISelHook = 0;
1974}
1975
1976multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1977                                    RegisterClass dst_rc,
1978                                    int channels> {
1979  def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32>,
1980            MIMG_Mask<asm#"_V1", channels>;
1981  def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1982            MIMG_Mask<asm#"_V2", channels>;
1983  def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1984            MIMG_Mask<asm#"_V4", channels>;
1985  def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1986            MIMG_Mask<asm#"_V8", channels>;
1987  def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1988            MIMG_Mask<asm#"_V16", channels>;
1989}
1990
1991multiclass MIMG_Gather <bits<7> op, string asm> {
1992  defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1>;
1993  defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1994  defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1995  defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1996}
1997
1998//===----------------------------------------------------------------------===//
1999// Vector instruction mappings
2000//===----------------------------------------------------------------------===//
2001
2002// Maps an opcode in e32 form to its e64 equivalent
2003def getVOPe64 : InstrMapping {
2004  let FilterClass = "VOP";
2005  let RowFields = ["OpName"];
2006  let ColFields = ["Size"];
2007  let KeyCol = ["4"];
2008  let ValueCols = [["8"]];
2009}
2010
2011// Maps an opcode in e64 form to its e32 equivalent
2012def getVOPe32 : InstrMapping {
2013  let FilterClass = "VOP";
2014  let RowFields = ["OpName"];
2015  let ColFields = ["Size"];
2016  let KeyCol = ["8"];
2017  let ValueCols = [["4"]];
2018}
2019
2020// Maps an original opcode to its commuted version
2021def getCommuteRev : InstrMapping {
2022  let FilterClass = "VOP2_REV";
2023  let RowFields = ["RevOp"];
2024  let ColFields = ["IsOrig"];
2025  let KeyCol = ["1"];
2026  let ValueCols = [["0"]];
2027}
2028
2029def getMaskedMIMGOp : InstrMapping {
2030  let FilterClass = "MIMG_Mask";
2031  let RowFields = ["Op"];
2032  let ColFields = ["Channels"];
2033  let KeyCol = ["4"];
2034  let ValueCols = [["1"], ["2"], ["3"] ];
2035}
2036
2037// Maps an commuted opcode to its original version
2038def getCommuteOrig : InstrMapping {
2039  let FilterClass = "VOP2_REV";
2040  let RowFields = ["RevOp"];
2041  let ColFields = ["IsOrig"];
2042  let KeyCol = ["0"];
2043  let ValueCols = [["1"]];
2044}
2045
2046def getMCOpcodeGen : InstrMapping {
2047  let FilterClass = "SIMCInstr";
2048  let RowFields = ["PseudoInstr"];
2049  let ColFields = ["Subtarget"];
2050  let KeyCol = [!cast<string>(SISubtarget.NONE)];
2051  let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2052}
2053
2054def getAddr64Inst : InstrMapping {
2055  let FilterClass = "MUBUFAddr64Table";
2056  let RowFields = ["OpName"];
2057  let ColFields = ["IsAddr64"];
2058  let KeyCol = ["0"];
2059  let ValueCols = [["1"]];
2060}
2061
2062// Maps an atomic opcode to its version with a return value.
2063def getAtomicRetOp : InstrMapping {
2064  let FilterClass = "AtomicNoRet";
2065  let RowFields = ["NoRetOp"];
2066  let ColFields = ["IsRet"];
2067  let KeyCol = ["0"];
2068  let ValueCols = [["1"]];
2069}
2070
2071// Maps an atomic opcode to its returnless version.
2072def getAtomicNoRetOp : InstrMapping {
2073  let FilterClass = "AtomicNoRet";
2074  let RowFields = ["NoRetOp"];
2075  let ColFields = ["IsRet"];
2076  let KeyCol = ["1"];
2077  let ValueCols = [["0"]];
2078}
2079
2080include "SIInstructions.td"
2081include "CIInstructions.td"
2082include "VIInstructions.td"
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