source: icGREP/icgrep-devel/llvm-3.5.0.src/test/CodeGen/R600/or.ll @ 4574

Last change on this file since 4574 was 4574, checked in by cameron, 4 years ago

Updating to LLVM 3.6

File size: 6.1 KB
Line 
1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
2;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
3
4; EG-LABEL: {{^}}or_v2i32:
5; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
6; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
7
8; SI-LABEL: {{^}}or_v2i32:
9; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
10; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
11
12define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
13  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
14  %a = load <2 x i32> addrspace(1) * %in
15  %b = load <2 x i32> addrspace(1) * %b_ptr
16  %result = or <2 x i32> %a, %b
17  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
18  ret void
19}
20
21; EG-LABEL: {{^}}or_v4i32:
22; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
23; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
24; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
26
27; SI-LABEL: {{^}}or_v4i32:
28; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
30; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32
33define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
34  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
35  %a = load <4 x i32> addrspace(1) * %in
36  %b = load <4 x i32> addrspace(1) * %b_ptr
37  %result = or <4 x i32> %a, %b
38  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
39  ret void
40}
41
42; SI-LABEL: {{^}}scalar_or_i32:
43; SI: s_or_b32
44define void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
45  %or = or i32 %a, %b
46  store i32 %or, i32 addrspace(1)* %out
47  ret void
48}
49
50; SI-LABEL: {{^}}vector_or_i32:
51; SI: v_or_b32_e32 v{{[0-9]}}
52define void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
53  %loada = load i32 addrspace(1)* %a
54  %or = or i32 %loada, %b
55  store i32 %or, i32 addrspace(1)* %out
56  ret void
57}
58
59; SI-LABEL: {{^}}scalar_or_literal_i32:
60; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
61define void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
62  %or = or i32 %a, 99999
63  store i32 %or, i32 addrspace(1)* %out, align 4
64  ret void
65}
66
67; SI-LABEL: {{^}}vector_or_literal_i32:
68; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
69define void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
70  %loada = load i32 addrspace(1)* %a, align 4
71  %or = or i32 %loada, 65535
72  store i32 %or, i32 addrspace(1)* %out, align 4
73  ret void
74}
75
76; SI-LABEL: {{^}}vector_or_inline_immediate_i32:
77; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
78define void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
79  %loada = load i32 addrspace(1)* %a, align 4
80  %or = or i32 %loada, 4
81  store i32 %or, i32 addrspace(1)* %out, align 4
82  ret void
83}
84
85; EG-LABEL: {{^}}scalar_or_i64:
86; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
87; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
88; SI-LABEL: {{^}}scalar_or_i64:
89; SI: s_or_b64
90define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
91  %or = or i64 %a, %b
92  store i64 %or, i64 addrspace(1)* %out
93  ret void
94}
95
96; SI-LABEL: {{^}}vector_or_i64:
97; SI: v_or_b32_e32 v{{[0-9]}}
98; SI: v_or_b32_e32 v{{[0-9]}}
99define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
100  %loada = load i64 addrspace(1)* %a, align 8
101  %loadb = load i64 addrspace(1)* %a, align 8
102  %or = or i64 %loada, %loadb
103  store i64 %or, i64 addrspace(1)* %out
104  ret void
105}
106
107; SI-LABEL: {{^}}scalar_vector_or_i64:
108; SI: v_or_b32_e32 v{{[0-9]}}
109; SI: v_or_b32_e32 v{{[0-9]}}
110define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
111  %loada = load i64 addrspace(1)* %a
112  %or = or i64 %loada, %b
113  store i64 %or, i64 addrspace(1)* %out
114  ret void
115}
116
117; SI-LABEL: {{^}}vector_or_i64_loadimm:
118; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
119; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x146f
120; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
121; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
122; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
123; SI: s_endpgm
124define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
125  %loada = load i64 addrspace(1)* %a, align 8
126  %or = or i64 %loada, 22470723082367
127  store i64 %or, i64 addrspace(1)* %out
128  ret void
129}
130
131; FIXME: The or 0 should really be removed.
132; SI-LABEL: {{^}}vector_or_i64_imm:
133; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
134; SI: v_or_b32_e32 {{v[0-9]+}}, 8, v[[LO_VREG]]
135; SI: v_or_b32_e32 {{v[0-9]+}}, 0, {{.*}}
136; SI: s_endpgm
137define void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
138  %loada = load i64 addrspace(1)* %a, align 8
139  %or = or i64 %loada, 8
140  store i64 %or, i64 addrspace(1)* %out
141  ret void
142}
143
144; SI-LABEL: {{^}}trunc_i64_or_to_i32:
145; SI: s_load_dword s[[SREG0:[0-9]+]]
146; SI: s_load_dword s[[SREG1:[0-9]+]]
147; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
148; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]]
149; SI: buffer_store_dword [[VRESULT]],
150define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
151  %add = or i64 %b, %a
152  %trunc = trunc i64 %add to i32
153  store i32 %trunc, i32 addrspace(1)* %out, align 8
154  ret void
155}
156
157; EG-CHECK: {{^}}or_i1:
158; EG-CHECK: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
159
160; SI-CHECK: {{^}}or_i1:
161; SI-CHECK: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
162define void @or_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
163  %a = load float addrspace(1) * %in0
164  %b = load float addrspace(1) * %in1
165  %acmp = fcmp oge float %a, 0.000000e+00
166  %bcmp = fcmp oge float %b, 0.000000e+00
167  %or = or i1 %acmp, %bcmp
168  %result = select i1 %or, float %a, float %b
169  store float %result, float addrspace(1)* %out
170  ret void
171}
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