source: icGREP/icgrep-devel/llvm-3.6.1.src/CREDITS.TXT @ 4721

Last change on this file since 4721 was 4574, checked in by cameron, 4 years ago

Updating to LLVM 3.6

File size: 10.7 KB
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1This file is a partial list of people who have contributed to the LLVM
2project.  If you have contributed a patch or made some other contribution to
3LLVM, please submit a patch to this file to add yourself, and it will be
4done!
5
6The list is sorted by surname and formatted to allow easy grepping and
7beautification by scripts.  The fields are: name (N), email (E), web-address
8(W), PGP key ID and fingerprint (P), description (D), snail-mail address
9(S), and (I) IRC handle.
10
11
12N: Vikram Adve
13E: vadve@cs.uiuc.edu
14W: http://www.cs.uiuc.edu/~vadve/
15D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
16
17N: Owen Anderson
18E: resistor@mac.com
19D: LCSSA pass and related LoopUnswitch work
20D: GVNPRE pass, DataLayout refactoring, random improvements
21
22N: Henrik Bach
23D: MingW Win32 API portability layer
24
25N: Aaron Ballman
26E: aaron@aaronballman.com
27D: __declspec attributes, Windows support, general bug fixing
28
29N: Nate Begeman
30E: natebegeman@mac.com
31D: PowerPC backend developer
32D: Target-independent code generator and analysis improvements
33
34N: Daniel Berlin
35E: dberlin@dberlin.org
36D: ET-Forest implementation.
37D: Sparse bitmap
38
39N: David Blaikie
40E: dblaikie@gmail.com
41D: General bug fixing/fit & finish, mostly in Clang
42
43N: Neil Booth
44E: neil@daikokuya.co.uk
45D: APFloat implementation.
46
47N: Misha Brukman
48E: brukman+llvm@uiuc.edu
49W: http://misha.brukman.net
50D: Portions of X86 and Sparc JIT compilers, PowerPC backend
51D: Incremental bitcode loader
52
53N: Cameron Buschardt
54E: buschard@uiuc.edu
55D: The `mem2reg' pass - promotes values stored in memory to registers
56
57N: Brendon Cahoon
58E: bcahoon@codeaurora.org
59D: Loop unrolling with run-time trip counts.
60
61N: Chandler Carruth
62E: chandlerc@gmail.com
63E: chandlerc@google.com
64D: Hashing algorithms and interfaces
65D: Inline cost analysis
66D: Machine block placement pass
67D: SROA
68
69N: Casey Carter
70E: ccarter@uiuc.edu
71D: Fixes to the Reassociation pass, various improvement patches
72
73N: Evan Cheng
74E: evan.cheng@apple.com
75D: ARM and X86 backends
76D: Instruction scheduler improvements
77D: Register allocator improvements
78D: Loop optimizer improvements
79D: Target-independent code generator improvements
80
81N: Dan Villiom Podlaski Christiansen
82E: danchr@gmail.com
83E: danchr@cs.au.dk
84W: http://villiom.dk
85D: LLVM Makefile improvements
86D: Clang diagnostic & driver tweaks
87S: Aarhus, Denmark
88
89N: Jeff Cohen
90E: jeffc@jolt-lang.org
91W: http://jolt-lang.org
92D: Native Win32 API portability layer
93
94N: John T. Criswell
95E: criswell@uiuc.edu
96D: Original Autoconf support, documentation improvements, bug fixes
97
98N: Anshuman Dasgupta
99E: adasgupt@codeaurora.org
100D: Deterministic finite automaton based infrastructure for VLIW packetization
101
102N: Stefanus Du Toit
103E: stefanus.du.toit@intel.com
104D: Bug fixes and minor improvements
105
106N: Rafael Avila de Espindola
107E: rafael.espindola@gmail.com
108D: The ARM backend
109
110N: Dave Estes
111E: cestes@codeaurora.org
112D: AArch64 machine description for Cortex-A53
113
114N: Alkis Evlogimenos
115E: alkis@evlogimenos.com
116D: Linear scan register allocator, many codegen improvements, Java frontend
117
118N: Hal Finkel
119E: hfinkel@anl.gov
120D: Basic-block autovectorization, PowerPC backend improvements
121
122N: Eric Fiselier
123E: eric@efcs.ca
124D: LIT patches and documentation.
125
126N: Ryan Flynn
127E: pizza@parseerror.com
128D: Miscellaneous bug fixes
129
130N: Brian Gaeke
131E: gaeke@uiuc.edu
132W: http://www.students.uiuc.edu/~gaeke/
133D: Portions of X86 static and JIT compilers; initial SparcV8 backend
134D: Dynamic trace optimizer
135D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
136
137N: Nicolas Geoffray
138E: nicolas.geoffray@lip6.fr
139W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
140D: PPC backend fixes for Linux
141
142N: Louis Gerbarg
143E: lgg@apple.com
144D: Portions of the PowerPC backend
145
146N: Saem Ghani
147E: saemghani@gmail.com
148D: Callgraph class cleanups
149
150N: Mikhail Glushenkov
151E: foldr@codedgers.com
152D: Author of llvmc2
153
154N: Dan Gohman
155E: dan433584@gmail.com
156D: Miscellaneous bug fixes
157
158N: David Goodwin
159E: david@goodwinz.net
160D: Thumb-2 code generator
161
162N: David Greene
163E: greened@obbligato.org
164D: Miscellaneous bug fixes
165D: Register allocation refactoring
166
167N: Gabor Greif
168E: ggreif@gmail.com
169D: Improvements for space efficiency
170
171N: James Grosbach
172E: grosbach@apple.com
173I: grosbach
174D: SjLj exception handling support
175D: General fixes and improvements for the ARM back-end
176D: MCJIT
177D: ARM integrated assembler and assembly parser
178D: Led effort for the backend formerly known as ARM64
179
180N: Lang Hames
181E: lhames@gmail.com
182D: PBQP-based register allocator
183
184N: Gordon Henriksen
185E: gordonhenriksen@mac.com
186D: Pluggable GC support
187D: C interface
188D: Ocaml bindings
189
190N: Raul Fernandes Herbster
191E: raul@dsc.ufcg.edu.br
192D: JIT support for ARM
193
194N: Paolo Invernizzi
195E: arathorn@fastwebnet.it
196D: Visual C++ compatibility fixes
197
198N: Patrick Jenkins
199E: patjenk@wam.umd.edu
200D: Nightly Tester
201
202N: Dale Johannesen
203E: dalej@apple.com
204D: ARM constant islands improvements
205D: Tail merging improvements
206D: Rewrite X87 back end
207D: Use APFloat for floating point constants widely throughout compiler
208D: Implement X87 long double
209
210N: Brad Jones
211E: kungfoomaster@nondot.org
212D: Support for packed types
213
214N: Rod Kay
215E: rkay@auroraux.org
216D: Author of LLVM Ada bindings
217
218N: Eric Kidd
219W: http://randomhacks.net/
220D: llvm-config script
221
222N: Anton Korobeynikov
223E: asl@math.spbu.ru
224D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
225D: x86/linux PIC codegen, aliases, regparm/visibility attributes
226D: Switch lowering refactoring
227
228N: Sumant Kowshik
229E: kowshik@uiuc.edu
230D: Author of the original C backend
231
232N: Benjamin Kramer
233E: benny.kra@gmail.com
234D: Miscellaneous bug fixes
235
236N: Sundeep Kushwaha
237E: sundeepk@codeaurora.org
238D: Implemented DFA-based target independent VLIW packetizer
239
240N: Christopher Lamb
241E: christopher.lamb@gmail.com
242D: aligned load/store support, parts of noalias and restrict support
243D: vreg subreg infrastructure, X86 codegen improvements based on subregs
244D: address spaces
245
246N: Jim Laskey
247E: jlaskey@apple.com
248D: Improvements to the PPC backend, instruction scheduling
249D: Debug and Dwarf implementation
250D: Auto upgrade mangler
251D: llvm-gcc4 svn wrangler
252
253N: Chris Lattner
254E: sabre@nondot.org
255W: http://nondot.org/~sabre/
256D: Primary architect of LLVM
257
258N: Tanya Lattner (Tanya Brethour)
259E: tonic@nondot.org
260W: http://nondot.org/~tonic/
261D: The initial llvm-ar tool, converted regression testsuite to dejagnu
262D: Modulo scheduling in the SparcV9 backend
263D: Release manager (1.7+)
264
265N: Sylvestre Ledru
266E: sylvestre@debian.org
267W: http://sylvestre.ledru.info/
268W: http://llvm.org/apt/
269D: Debian and Ubuntu packaging
270D: Continuous integration with jenkins
271
272N: Andrew Lenharth
273E: alenhar2@cs.uiuc.edu
274W: http://www.lenharth.org/~andrewl/
275D: Alpha backend
276D: Sampling based profiling
277
278N: Nick Lewycky
279E: nicholas@mxc.ca
280D: PredicateSimplifier pass
281
282N: Tony Linthicum, et. al.
283E: tlinth@codeaurora.org
284D: Backend for Qualcomm's Hexagon VLIW processor.
285
286N: Bruno Cardoso Lopes
287E: bruno.cardoso@gmail.com
288I: bruno
289W: http://brunocardoso.cc
290D: Mips backend
291D: Random ARM integrated assembler and assembly parser improvements
292D: General X86 AVX1 support
293
294N: Duraid Madina
295E: duraid@octopus.com.au
296W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
297D: IA64 backend, BigBlock register allocator
298
299N: John McCall
300E: rjmccall@apple.com
301D: Clang semantic analysis and IR generation
302
303N: Michael McCracken
304E: michael.mccracken@gmail.com
305D: Line number support for llvmgcc
306
307N: Vladimir Merzliakov
308E: wanderer@rsu.ru
309D: Test suite fixes for FreeBSD
310
311N: Scott Michel
312E: scottm@aero.org
313D: Added STI Cell SPU backend.
314
315N: Kai Nacke
316E: kai@redstar.de
317D: Support for implicit TLS model used with MS VC runtime
318D: Dumping of Win64 EH structures
319
320N: Takumi Nakamura
321E: geek4civic@gmail.com
322E: chapuni@hf.rim.or.jp
323D: Cygwin and MinGW support.
324D: Win32 tweaks.
325S: Yokohama, Japan
326
327N: Edward O'Callaghan
328E: eocallaghan@auroraux.org
329W: http://www.auroraux.org
330D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
331D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
332D: and error clean ups.
333
334N: Morten Ofstad
335E: morten@hue.no
336D: Visual C++ compatibility fixes
337
338N: Jakob Stoklund Olesen
339E: stoklund@2pi.dk
340D: Machine code verifier
341D: Blackfin backend
342D: Fast register allocator
343D: Greedy register allocator
344
345N: Richard Osborne
346E: richard@xmos.com
347D: XCore backend
348
349N: Devang Patel
350E: dpatel@apple.com
351D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
352D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
353D: Optimizer improvements, Loop Index Split
354
355N: Ana Pazos
356E: apazos@codeaurora.org
357D: Fixes and improvements to the AArch64 backend
358
359N: Wesley Peck
360E: peckw@wesleypeck.com
361W: http://wesleypeck.com/
362D: MicroBlaze backend
363
364N: Francois Pichet
365E: pichet2000@gmail.com
366D: MSVC support
367
368N: Vladimir Prus
369W: http://vladimir_prus.blogspot.com
370E: ghost@cs.msu.su
371D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
372
373N: Kalle Raiskila
374E: kalle.rasikila@nokia.com
375D: Some bugfixes to CellSPU
376
377N: Xerxes Ranby
378E: xerxes@zafena.se
379D: Cmake dependency chain and various bug fixes
380
381N: Alex Rosenberg
382E: alexr@leftfield.org
383I: arosenberg
384D: ARM calling conventions rewrite, hard float support
385
386N: Chad Rosier
387E: mcrosier@codeaurora.org
388I: mcrosier
389D: AArch64 fast instruction selection pass
390D: Fixes and improvements to the ARM fast-isel pass
391D: Fixes and improvements to the AArch64 backend
392
393N: Nadav Rotem
394E: nrotem@apple.com
395D: X86 code generation improvements, Loop Vectorizer.
396
397N: Roman Samoilov
398E: roman@codedgers.com
399D: MSIL backend
400
401N: Duncan Sands
402E: baldrick@free.fr
403I: baldrick
404D: Ada support in llvm-gcc
405D: Dragonegg plugin
406D: Exception handling improvements
407D: Type legalizer rewrite
408
409N: Ruchira Sasanka
410E: sasanka@uiuc.edu
411D: Graph coloring register allocator for the Sparc64 backend
412
413N: Arnold Schwaighofer
414E: arnold.schwaighofer@gmail.com
415D: Tail call optimization for the x86 backend
416
417N: Shantonu Sen
418E: ssen@apple.com
419D: Miscellaneous bug fixes
420
421N: Anand Shukla
422E: ashukla@cs.uiuc.edu
423D: The `paths' pass
424
425N: Michael J. Spencer
426E: bigcheesegs@gmail.com
427D: Shepherding Windows COFF support into MC.
428D: Lots of Windows stuff.
429
430N: Reid Spencer
431E: rspencer@reidspencer.com
432W: http://reidspencer.com/
433D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
434
435N: Alp Toker
436E: alp@nuanti.com
437W: http://atoker.com/
438D: C++ frontend next generation standards implementation
439
440N: Craig Topper
441E: craig.topper@gmail.com
442D: X86 codegen and disassembler improvements. AVX2 support.
443
444N: Edwin Torok
445E: edwintorok@gmail.com
446D: Miscellaneous bug fixes
447
448N: Adam Treat
449E: manyoso@yahoo.com
450D: C++ bugs filed, and C++ front-end bug fixes.
451
452N: Lauro Ramos Venancio
453E: lauro.venancio@indt.org.br
454D: ARM backend improvements
455D: Thread Local Storage implementation
456
457N: Bill Wendling
458I: wendling
459E: isanbard@gmail.com
460D: Release manager, IR Linker, LTO
461D: Bunches of stuff
462
463N: Bob Wilson
464E: bob.wilson@acm.org
465D: Advanced SIMD (NEON) support in the ARM backend.
466
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