source: icGREP/icgrep-devel/llvm-3.6.1.src/lib/Target/Mips/Mips64InstrInfo.td @ 4664

Last change on this file since 4664 was 4664, checked in by cameron, 4 years ago

Upgrade LLVM to 3.6.1

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1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Mips Operand, Complex Patterns and Transformations Definitions.
16//===----------------------------------------------------------------------===//
17
18// Unsigned Operand
19def uimm16_64      : Operand<i64> {
20  let PrintMethod = "printUnsignedImm";
21}
22
23// Signed Operand
24def simm10_64 : Operand<i64>;
25
26def imm64: Operand<i64>;
27
28// Transformation Function - get Imm - 32.
29def Subtract32 : SDNodeXForm<imm, [{
30  return getImm(N, (unsigned)N->getZExtValue() - 32);
31}]>;
32
33// shamt must fit in 6 bits.
34def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
35
36// Node immediate fits as 10-bit sign extended on target immediate.
37// e.g. seqi, snei
38def immSExt10_64 : PatLeaf<(i64 imm),
39                           [{ return isInt<10>(N->getSExtValue()); }]>;
40
41def immZExt16_64 : PatLeaf<(i64 imm),
42                           [{ return isInt<16>(N->getZExtValue()); }]>;
43
44//===----------------------------------------------------------------------===//
45// Instructions specific format
46//===----------------------------------------------------------------------===//
47let usesCustomInserter = 1 in {
48  def ATOMIC_LOAD_ADD_I64  : Atomic2Ops<atomic_load_add_64, GPR64>;
49  def ATOMIC_LOAD_SUB_I64  : Atomic2Ops<atomic_load_sub_64, GPR64>;
50  def ATOMIC_LOAD_AND_I64  : Atomic2Ops<atomic_load_and_64, GPR64>;
51  def ATOMIC_LOAD_OR_I64   : Atomic2Ops<atomic_load_or_64, GPR64>;
52  def ATOMIC_LOAD_XOR_I64  : Atomic2Ops<atomic_load_xor_64, GPR64>;
53  def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
54  def ATOMIC_SWAP_I64      : Atomic2Ops<atomic_swap_64, GPR64>;
55  def ATOMIC_CMP_SWAP_I64  : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
56}
57
58/// Pseudo instructions for loading and storing accumulator registers.
59let isPseudo = 1, isCodeGenOnly = 1 in {
60  def LOAD_ACC128  : Load<"", ACC128>;
61  def STORE_ACC128 : Store<"", ACC128>;
62}
63
64//===----------------------------------------------------------------------===//
65// Instruction definition
66//===----------------------------------------------------------------------===//
67let DecoderNamespace = "Mips64" in {
68/// Arithmetic Instructions (ALU Immediate)
69def DADDi   : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
70              ISA_MIPS3_NOT_32R6_64R6;
71def DADDiu  : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
72                          immSExt16, add>,
73              ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
74
75let isCodeGenOnly = 1 in {
76def SLTi64  : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
77              SLTI_FM<0xa>;
78def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
79              SLTI_FM<0xb>;
80def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
81             ADDI_FM<0xc>;
82def ORi64   : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
83              ADDI_FM<0xd>;
84def XORi64  : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
85              ADDI_FM<0xe>;
86def LUi64   : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
87}
88
89/// Arithmetic Instructions (3-Operand, R-Type)
90def DADD   : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
91             ISA_MIPS3;
92def DADDu  : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
93             ISA_MIPS3;
94def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
95             ISA_MIPS3;
96def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
97             ISA_MIPS3;
98
99let isCodeGenOnly = 1 in {
100def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
101def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
102def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
103def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
104def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
105def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
106}
107
108/// Shift Instructions
109def DSLL   : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
110             SRA_FM<0x38, 0>, ISA_MIPS3;
111def DSRL   : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
112             SRA_FM<0x3a, 0>, ISA_MIPS3;
113def DSRA   : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
114             SRA_FM<0x3b, 0>, ISA_MIPS3;
115def DSLLV  : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
116             SRLV_FM<0x14, 0>, ISA_MIPS3;
117def DSRLV  : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
118             SRLV_FM<0x16, 0>, ISA_MIPS3;
119def DSRAV  : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
120             SRLV_FM<0x17, 0>, ISA_MIPS3;
121def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
122             SRA_FM<0x3c, 0>, ISA_MIPS3;
123def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
124             SRA_FM<0x3e, 0>, ISA_MIPS3;
125def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
126             SRA_FM<0x3f, 0>, ISA_MIPS3;
127
128// Rotate Instructions
129def DROTR  : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
130                              immZExt6>,
131             SRA_FM<0x3a, 1>, ISA_MIPS64R2;
132def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
133             SRLV_FM<0x16, 1>, ISA_MIPS64R2;
134def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
135              SRA_FM<0x3e, 1>, ISA_MIPS64R2;
136
137/// Load and Store Instructions
138///  aligned
139let isCodeGenOnly = 1 in {
140def LB64  : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
141def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
142def LH64  : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
143def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
144def LW64  : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
145def SB64  : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
146def SH64  : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
147def SW64  : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
148}
149
150def LWu   : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
151def LD    : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
152def SD    : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
153
154/// load/store left/right
155let isCodeGenOnly = 1 in {
156def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
157def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
158def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
159def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
160}
161
162def LDL   : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
163            ISA_MIPS3_NOT_32R6_64R6;
164def LDR   : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
165            ISA_MIPS3_NOT_32R6_64R6;
166def SDL   : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
167            ISA_MIPS3_NOT_32R6_64R6;
168def SDR   : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
169            ISA_MIPS3_NOT_32R6_64R6;
170
171/// Load-linked, Store-conditional
172def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
173def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
174
175/// Jump and Branch Instructions
176let isCodeGenOnly = 1 in {
177  def JR64   : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
178  def BEQ64  : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
179  def BNE64  : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
180  def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
181  def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
182  def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
183  def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
184  def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
185  def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
186  def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
187}
188
189def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
190def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
191
192/// Multiply and Divide Instructions.
193def DMULT  : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
194             MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
195def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
196             MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
197def PseudoDMULT  : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
198                                 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
199def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
200                                 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
201def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
202            MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
203def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
204            MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
205def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
206                                II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
207def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
208                                II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
209
210let isCodeGenOnly = 1 in {
211def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
212             ISA_MIPS3_NOT_32R6_64R6;
213def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
214             ISA_MIPS3_NOT_32R6_64R6;
215def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
216             ISA_MIPS3_NOT_32R6_64R6;
217def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
218             ISA_MIPS3_NOT_32R6_64R6;
219def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
220                   ISA_MIPS3_NOT_32R6_64R6;
221def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
222                   ISA_MIPS3_NOT_32R6_64R6;
223def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
224
225/// Sign Ext In Register Instructions.
226def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
227            ISA_MIPS32R2;
228def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
229            ISA_MIPS32R2;
230}
231
232/// Count Leading
233def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
234def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
235
236/// Double Word Swap Bytes/HalfWords
237def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
238def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
239
240def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
241
242let isCodeGenOnly = 1 in
243def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
244
245def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
246def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
247def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
248
249def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
250def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
251def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
252
253let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
254  def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
255                     "dsll\t$rd, $rt, 32", [], II_DSLL>;
256  def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
257                    "sll\t$rd, $rt, 0", [], II_SLL>;
258  def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
259                    "sll\t$rd, $rt, 0", [], II_SLL>;
260}
261
262// We need the following pseudo instruction to avoid offset calculation for
263// long branches.  See the comment in file MipsLongBranch.cpp for detailed
264// explanation.
265
266// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
267// where %PART may be %hi or %lo, depending on the relocation kind
268// that $tgt is annotated with.
269def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
270  (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
271
272// Cavium Octeon cmMIPS instructions
273let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
274    AdditionalPredicates = [HasCnMips] in {
275
276class Count1s<string opstr, RegisterOperand RO>:
277  InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
278         [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
279  let TwoOperandAliasConstraint = "$rd = $rs";
280}
281
282class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
283  InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
284         !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
285         [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
286         NoItinerary, FrmR, opstr> {
287  let TwoOperandAliasConstraint = "$rt = $rs";
288}
289
290class SetCC64_R<string opstr, PatFrag cond_op> :
291  InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
292         !strconcat(opstr, "\t$rd, $rs, $rt"),
293         [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
294                                             GPR64Opnd:$rt)))],
295         II_SEQ_SNE, FrmR, opstr> {
296  let TwoOperandAliasConstraint = "$rd = $rs";
297}
298
299class SetCC64_I<string opstr, PatFrag cond_op>:
300  InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
301         !strconcat(opstr, "\t$rt, $rs, $imm10"),
302         [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
303                                             immSExt10_64:$imm10)))],
304         II_SEQI_SNEI, FrmI, opstr> {
305  let TwoOperandAliasConstraint = "$rt = $rs";
306}
307
308// Unsigned Byte Add
309let Pattern = [(set GPR64Opnd:$rd,
310                    (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
311def BADDu  : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
312                              ADD_FM<0x1c, 0x28>;
313
314// Multiply Doubleword to GPR
315let Defs = [HI0, LO0, P0, P1, P2] in
316def DMUL  : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
317                              ADD_FM<0x1c, 0x03>;
318
319// Extract a signed bit field /+32
320def EXTS  : ExtsCins<"exts">, EXTS_FM<0x3a>;
321def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
322
323// Clear and insert a bit field /+32
324def CINS  : ExtsCins<"cins">, EXTS_FM<0x32>;
325def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
326
327// Move to multiplier/product register
328def MTM0   : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
329def MTM1   : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
330def MTM2   : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
331def MTP0   : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
332def MTP1   : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
333def MTP2   : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
334
335// Count Ones in a Word/Doubleword
336def POP   : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
337def DPOP  : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
338
339// Set on equal/not equal
340def SEQ   : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
341def SEQi  : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
342def SNE   : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
343def SNEi  : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
344
345// 192-bit x 64-bit Unsigned Multiply and Add
346let Defs = [P0, P1, P2] in
347def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
348                                  ADD_FM<0x1c, 0x11>;
349
350// 64-bit Unsigned Multiply and Add Move
351let Defs = [MPL0, P0, P1, P2] in
352def VMM0  : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
353                                ADD_FM<0x1c, 0x10>;
354
355// 64-bit Unsigned Multiply and Add
356let Defs = [MPL1, MPL2, P0, P1, P2] in
357def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
358                                 ADD_FM<0x1c, 0x0f>;
359
360}
361
362}
363
364//===----------------------------------------------------------------------===//
365//  Arbitrary patterns that map to one or more instructions
366//===----------------------------------------------------------------------===//
367
368// extended loads
369def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
370def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
371def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
372def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
373
374// hi/lo relocs
375def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
376def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
377def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
378def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
379def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
380def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
381
382def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
383def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
384def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
385def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
386def : MipsPat<(MipsLo tglobaltlsaddr:$in),
387              (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
388def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
389
390def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
391              (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
392def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
393              (DADDiu GPR64:$hi, tblockaddress:$lo)>;
394def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
395              (DADDiu GPR64:$hi, tjumptable:$lo)>;
396def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
397              (DADDiu GPR64:$hi, tconstpool:$lo)>;
398def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
399              (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
400
401def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
402def : WrapperPat<tconstpool, DADDiu, GPR64>;
403def : WrapperPat<texternalsym, DADDiu, GPR64>;
404def : WrapperPat<tblockaddress, DADDiu, GPR64>;
405def : WrapperPat<tjumptable, DADDiu, GPR64>;
406def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
407
408defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
409                  ZERO_64>;
410
411def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
412              (BLEZ64 i64:$lhs, bb:$dst)>;
413def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
414              (BGEZ64 i64:$lhs, bb:$dst)>;
415
416// setcc patterns
417defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
418defm : SetlePats<GPR64, SLT64, SLTu64>;
419defm : SetgtPats<GPR64, SLT64, SLTu64>;
420defm : SetgePats<GPR64, SLT64, SLTu64>;
421defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
422
423// truncate
424def : MipsPat<(trunc (assertsext GPR64:$src)),
425              (EXTRACT_SUBREG GPR64:$src, sub_32)>;
426def : MipsPat<(trunc (assertzext GPR64:$src)),
427              (EXTRACT_SUBREG GPR64:$src, sub_32)>;
428def : MipsPat<(i32 (trunc GPR64:$src)),
429              (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
430
431// 32-to-64-bit extension
432def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
433def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
434def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
435
436// Sign extend in register
437def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
438              (SLL64_64 GPR64:$src)>;
439
440// bswap MipsPattern
441def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
442
443// Carry pattern
444def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
445              (DSUBu GPR64:$lhs, GPR64:$rhs)>;
446let AdditionalPredicates = [NotDSP] in {
447  def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
448                (DADDu GPR64:$lhs, GPR64:$rhs)>;
449  def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
450                (DADDiu GPR64:$lhs, imm:$imm)>;
451}
452
453//===----------------------------------------------------------------------===//
454// Instruction aliases
455//===----------------------------------------------------------------------===//
456def : MipsInstAlias<"move $dst, $src",
457                    (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
458      GPR_64;
459def : MipsInstAlias<"daddu $rs, $rt, $imm",
460                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
461                    0>, ISA_MIPS3;
462def : MipsInstAlias<"dadd $rs, $rt, $imm",
463                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
464                    0>, ISA_MIPS3_NOT_32R6_64R6;
465def : MipsInstAlias<"daddu $rs, $imm",
466                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
467                    0>, ISA_MIPS3;
468def : MipsInstAlias<"dadd $rs, $imm",
469                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
470                    0>, ISA_MIPS3_NOT_32R6_64R6;
471def : MipsInstAlias<"dsll $rd, $rt, $rs",
472                    (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
473                    ISA_MIPS3;
474def : MipsInstAlias<"dsubu $rt, $rs, $imm",
475                    (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
476                            InvertedImOperand64:$imm), 0>, ISA_MIPS3;
477def : MipsInstAlias<"dsubi $rs, $rt, $imm",
478                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
479                           InvertedImOperand64:$imm),
480                    0>, ISA_MIPS3_NOT_32R6_64R6;
481def : MipsInstAlias<"dsubi $rs, $imm",
482                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
483                           InvertedImOperand64:$imm),
484                    0>, ISA_MIPS3_NOT_32R6_64R6;
485def : MipsInstAlias<"dsub $rs, $rt, $imm",
486                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
487                           InvertedImOperand64:$imm),
488                    0>, ISA_MIPS3_NOT_32R6_64R6;
489def : MipsInstAlias<"dsub $rs, $imm",
490                    (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
491                           InvertedImOperand64:$imm),
492                    0>, ISA_MIPS3_NOT_32R6_64R6;
493def : MipsInstAlias<"dsubu $rs, $imm",
494                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
495                            InvertedImOperand64:$imm),
496                    0>, ISA_MIPS3;
497def : MipsInstAlias<"dsra $rd, $rt, $rs",
498                    (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
499                    ISA_MIPS3;
500def : MipsInstAlias<"dsrl $rd, $rt, $rs",
501                    (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
502                    ISA_MIPS3;
503
504class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
505  MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
506                     !strconcat(instr_asm, "\t$rt, $imm64")> ;
507def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
508
509/// Move between CPU and coprocessor registers
510let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
511def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
512def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
513def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
514def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
515}
516
517// Two operand (implicit 0 selector) versions:
518def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
519def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
520def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
521def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
522
523let Predicates = [HasMips64, HasCnMips] in {
524def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
525def : MipsInstAlias<"syncs",      (SYNC 0x6), 0>;
526def : MipsInstAlias<"syncw",      (SYNC 0x4), 0>;
527def : MipsInstAlias<"syncws",     (SYNC 0x5), 0>;
528}
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