source: icGREP/icgrep-devel/llvm-3.6.1.src/test/CodeGen/R600/fneg-fabs.f64.ll @ 4664

Last change on this file since 4664 was 4664, checked in by cameron, 4 years ago

Upgrade LLVM to 3.6.1

File size: 4.3 KB
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1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3
4; FIXME: Check something here. Currently it seems fabs + fneg aren't
5; into 2 modifiers, although theoretically that should work.
6
7; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64:
8; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x7fffffff
9; SI: v_and_b32_e32 v[[FABS:[0-9]+]], {{s[0-9]+}}, [[IMMREG]]
10; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}}
11define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
12  %fabs = call double @llvm.fabs.f64(double %x)
13  %fsub = fsub double -0.000000e+00, %fabs
14  %fadd = fadd double %y, %fsub
15  store double %fadd, double addrspace(1)* %out, align 8
16  ret void
17}
18
19define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
20  %x = load double addrspace(1)* %xptr, align 8
21  %y = load double addrspace(1)* %xptr, align 8
22  %fabs = call double @llvm.fabs.f64(double %x)
23  %fsub = fsub double -0.000000e+00, %fabs
24  %fadd = fadd double %y, %fsub
25  store double %fadd, double addrspace(1)* %out, align 8
26  ret void
27}
28
29; FUNC-LABEL: {{^}}fneg_fabs_fmul_f64:
30; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}|
31define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
32  %fabs = call double @llvm.fabs.f64(double %x)
33  %fsub = fsub double -0.000000e+00, %fabs
34  %fmul = fmul double %y, %fsub
35  store double %fmul, double addrspace(1)* %out, align 8
36  ret void
37}
38
39; FUNC-LABEL: {{^}}fneg_fabs_free_f64:
40define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
41  %bc = bitcast i64 %in to double
42  %fabs = call double @llvm.fabs.f64(double %bc)
43  %fsub = fsub double -0.000000e+00, %fabs
44  store double %fsub, double addrspace(1)* %out
45  ret void
46}
47
48; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64:
49; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
50; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
51define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
52  %bc = bitcast i64 %in to double
53  %fabs = call double @fabs(double %bc)
54  %fsub = fsub double -0.000000e+00, %fabs
55  store double %fsub, double addrspace(1)* %out
56  ret void
57}
58
59; FUNC-LABEL: {{^}}fneg_fabs_f64:
60; SI: s_load_dwordx2
61; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
62; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
63; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
64; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
65; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
66define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
67  %fabs = call double @llvm.fabs.f64(double %in)
68  %fsub = fsub double -0.000000e+00, %fabs
69  store double %fsub, double addrspace(1)* %out, align 8
70  ret void
71}
72
73; FUNC-LABEL: {{^}}fneg_fabs_v2f64:
74; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
75; SI-NOT: 0x80000000
76; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
77; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
78define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
79  %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
80  %fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
81  store <2 x double> %fsub, <2 x double> addrspace(1)* %out
82  ret void
83}
84
85; FUNC-LABEL: {{^}}fneg_fabs_v4f64:
86; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
87; SI-NOT: 0x80000000
88; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
89; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
90; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
91; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
92define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
93  %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
94  %fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
95  store <4 x double> %fsub, <4 x double> addrspace(1)* %out
96  ret void
97}
98
99declare double @fabs(double) readnone
100declare double @llvm.fabs.f64(double) readnone
101declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
102declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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