source: icGREP/icgrep-devel/llvm-3.6.1.src/test/CodeGen/R600/llvm.log2.ll @ 4664

Last change on this file since 4664 was 4664, checked in by cameron, 4 years ago

Upgrade LLVM to 3.6.1

File size: 2.8 KB
RevLine 
[4664]1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
2;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
3;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s --check-prefix=SI --check-prefix=FUNC
4;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
[4279]5
[4574]6;FUNC-LABEL: {{^}}test:
[4664]7;EG: LOG_IEEE
8;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
9;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
10;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
11;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
12;SI: v_log_f32
[4279]13
14define void @test(float addrspace(1)* %out, float %in) {
15entry:
16   %0 = call float @llvm.log2.f32(float %in)
17   store float %0, float addrspace(1)* %out
18   ret void
19}
20
[4574]21;FUNC-LABEL: {{^}}testv2:
[4664]22;EG: LOG_IEEE
23;EG: LOG_IEEE
[4279]24; FIXME: We should be able to merge these packets together on Cayman so we
25; have a maximum of 4 instructions.
[4664]26;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
27;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
28;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
29;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
30;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
31;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
32;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
33;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
34;SI: v_log_f32
35;SI: v_log_f32
[4279]36
37define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
38entry:
39  %0 = call <2 x float> @llvm.log2.v2f32(<2 x float> %in)
40  store <2 x float> %0, <2 x float> addrspace(1)* %out
41  ret void
42}
43
[4574]44;FUNC-LABEL: {{^}}testv4:
[4664]45;EG: LOG_IEEE
46;EG: LOG_IEEE
47;EG: LOG_IEEE
48;EG: LOG_IEEE
[4279]49; FIXME: We should be able to merge these packets together on Cayman so we
50; have a maximum of 4 instructions.
[4664]51;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
52;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
53;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
54;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
55;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
56;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
57;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
58;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
59;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
60;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
61;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
62;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
63;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
64;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
65;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
66;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
67;SI: v_log_f32
68;SI: v_log_f32
69;SI: v_log_f32
70;SI: v_log_f32
[4279]71define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
72entry:
73  %0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in)
74  store <4 x float> %0, <4 x float> addrspace(1)* %out
75  ret void
76}
77
78declare float @llvm.log2.f32(float) readnone
79declare <2 x float> @llvm.log2.v2f32(<2 x float>) readnone
80declare <4 x float> @llvm.log2.v4f32(<4 x float>) readnone
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