source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-aapcs.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 4.9 KB
Line 
1; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
2
3@var = global i32 0, align 4
4
5; CHECK-LABEL: @test_i128_align
6define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
7  store i32 %after, i32* @var, align 4
8; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
9
10  ret i128 %arg
11; CHECK: mov x0, x2
12; CHECK: mov x1, x3
13}
14
15; CHECK-LABEL: @test_i64x2_align
16define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
17  store i32 %after, i32* @var, align 4
18; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
19
20  ret [2 x i64] %arg
21; CHECK: mov x0, x1
22; CHECK: mov x1, x2
23}
24
25@var64 = global i64 0, align 8
26
27  ; Check stack slots are 64-bit at all times.
28define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short,
29                                i32 %int, i64 %long) {
30  %ext_bool = zext i1 %bool to i64
31  store volatile i64 %ext_bool, i64* @var64, align 8
32; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
33
34  ; Part of last store. Blasted scheduler.
35; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
36
37; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
38; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
39
40  %ext_char = zext i8 %char to i64
41  store volatile i64 %ext_char, i64* @var64, align 8
42; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8]
43; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
44
45  %ext_short = zext i16 %short to i64
46  store volatile i64 %ext_short, i64* @var64, align 8
47; CHECK: ldrh w[[EXT:[0-9]+]], [sp, #16]
48; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
49
50  %ext_int = zext i32 %int to i64
51  store volatile i64 %ext_int, i64* @var64, align 8
52; CHECK: ldr{{b?}} w[[EXT:[0-9]+]], [sp, #24]
53; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
54
55  store volatile i64 %long, i64* @var64, align 8
56; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
57
58  ret void
59}
60
61; Make sure the callee does extensions (in the absence of zext/sext
62; keyword on args) while we're here.
63
64define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
65  %ext_bool = zext i1 %bool to i64
66  store volatile i64 %ext_bool, i64* @var64
67; CHECK: and w[[EXT:[0-9]+]], w0, #0x1
68; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
69
70  %ext_char = sext i8 %char to i64
71  store volatile i64 %ext_char, i64* @var64
72; CHECK: sxtb [[EXT:x[0-9]+]], w1
73; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
74
75  %ext_short = zext i16 %short to i64
76  store volatile i64 %ext_short, i64* @var64
77; CHECK: and w[[EXT:[0-9]+]], w2, #0xffff
78; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
79
80  %ext_int = zext i32 %int to i64
81  store volatile i64 %ext_int, i64* @var64
82; CHECK: mov w[[EXT:[0-9]+]], w3
83; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
84
85  ret void
86}
87
88declare void @variadic(i32 %a, ...)
89
90  ; Under AAPCS variadic functions have the same calling convention as
91  ; others. The extra arguments should go in registers rather than on the stack.
92define void @test_variadic() {
93  call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
94; CHECK: fmov d0, #2.0
95; CHECK: orr w1, wzr, #0x1
96; CHECK: bl variadic
97  ret void
98}
99
100; We weren't marking x7 as used after deciding that the i128 didn't fit into
101; registers and putting the first half on the stack, so the *second* half went
102; into x7. Yuck!
103define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
104; CHECK-LABEL: test_i128_shadow:
105; CHECK: ldp x0, x1, [sp]
106
107  ret i128 %sp
108}
109
110; This test is to check if fp128 can be correctly handled on stack.
111define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) {
112; CHECK-LABEL: test_fp128:
113; CHECK: ldr {{q[0-9]+}}, [sp]
114  ret fp128 %arg1
115}
116
117; Check if VPR can be correctly pass by stack.
118define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {
119entry:
120; CHECK-LABEL: test_vreg_stack:
121; CHECK: ldr {{q[0-9]+}}, [sp]
122  ret <2 x double> %varg_stack;
123}
124
125; Check that f16 can be passed and returned (ACLE 2.0 extension)
126define half @test_half(float, half %arg) {
127; CHECK-LABEL: test_half:
128; CHECK: mov v0.16b, v1.16b
129  ret half %arg;
130}
131
132; Check that f16 constants are materialized correctly
133define half @test_half_const() {
134; CHECK-LABEL: test_half_const:
135; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]
136  ret half 0xH4248
137}
138
139; Check that v4f16 can be passed and returned in registers
140define <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
141; CHECK-LABEL: test_v4_half_register:
142; CHECK: mov v0.16b, v1.16b
143  ret <4 x half> %arg;
144}
145
146; Check that v8f16 can be passed and returned in registers
147define <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
148; CHECK-LABEL: test_v8_half_register:
149; CHECK: mov v0.16b, v1.16b
150  ret <8 x half> %arg;
151}
152
153; Check that v4f16 can be passed and returned on the stack
154define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {
155; CHECK-LABEL: test_v4_half_stack:
156; CHECK: ldr d0, [sp]
157  ret <4 x half> %arg;
158}
159
160; Check that v8f16 can be passed and returned on the stack
161define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {
162; CHECK-LABEL: test_v8_half_stack:
163; CHECK: ldr q0, [sp]
164  ret <8 x half> %arg;
165}
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