source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-crypto.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 5.4 KB
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1; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
2
3declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
4declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
5declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
6declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
7
8define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
9; CHECK-LABEL: test_aese:
10; CHECK: aese.16b v0, v1
11  %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
12  ret <16 x i8> %res
13}
14
15define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
16; CHECK-LABEL: test_aesd:
17; CHECK: aesd.16b v0, v1
18  %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
19  ret <16 x i8> %res
20}
21
22define <16 x i8> @test_aesmc(<16 x i8> %data) {
23; CHECK-LABEL: test_aesmc:
24; CHECK: aesmc.16b v0, v0
25 %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
26  ret <16 x i8> %res
27}
28
29define <16 x i8> @test_aesimc(<16 x i8> %data) {
30; CHECK-LABEL: test_aesimc:
31; CHECK: aesimc.16b v0, v0
32 %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
33  ret <16 x i8> %res
34}
35
36declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
37declare <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
38declare <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
39declare i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
40declare <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
41declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
42
43define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
44; CHECK-LABEL: test_sha1c:
45; CHECK: fmov [[HASH_E:s[0-9]+]], w0
46; CHECK: sha1c.4s q0, [[HASH_E]], v1
47  %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
48  ret <4 x i32> %res
49}
50
51; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
52define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
53; CHECK-LABEL: test_sha1c_in_a_row:
54; CHECK: fmov [[HASH_E:s[0-9]+]], w0
55; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
56; CHECK-NOT: fmov
57; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
58  %res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
59  %extract = extractelement <4 x i32> %res, i32 0
60  %res2 = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
61  ret <4 x i32> %res2
62}
63
64define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
65; CHECK-LABEL: test_sha1p:
66; CHECK: fmov [[HASH_E:s[0-9]+]], w0
67; CHECK: sha1p.4s q0, [[HASH_E]], v1
68  %res = call <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
69  ret <4 x i32> %res
70}
71
72define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
73; CHECK-LABEL: test_sha1m:
74; CHECK: fmov [[HASH_E:s[0-9]+]], w0
75; CHECK: sha1m.4s q0, [[HASH_E]], v1
76  %res = call <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
77  ret <4 x i32> %res
78}
79
80define i32 @test_sha1h(i32 %hash_e) {
81; CHECK-LABEL: test_sha1h:
82; CHECK: fmov [[HASH_E:s[0-9]+]], w0
83; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
84; CHECK: fmov w0, [[RES]]
85  %res = call i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
86  ret i32 %res
87}
88
89define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
90; CHECK-LABEL: test_sha1su0:
91; CHECK: sha1su0.4s v0, v1, v2
92  %res = call <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
93  ret <4 x i32> %res
94}
95
96define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
97; CHECK-LABEL: test_sha1su1:
98; CHECK: sha1su1.4s v0, v1
99  %res = call <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
100  ret <4 x i32> %res
101}
102
103declare <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
104declare <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
105declare <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
106declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
107
108define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
109; CHECK-LABEL: test_sha256h:
110; CHECK: sha256h.4s q0, q1, v2
111  %res = call <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
112  ret <4 x i32> %res
113}
114
115define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
116; CHECK-LABEL: test_sha256h2:
117; CHECK: sha256h2.4s q0, q1, v2
118
119  %res = call <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
120  ret <4 x i32> %res
121}
122
123define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
124; CHECK-LABEL: test_sha256su0:
125; CHECK: sha256su0.4s v0, v1
126  %res = call <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
127  ret <4 x i32> %res
128}
129
130define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
131; CHECK-LABEL: test_sha256su1:
132; CHECK: sha256su1.4s v0, v1, v2
133  %res = call <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
134  ret <4 x i32> %res
135}
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