1 | ; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \ |
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2 | ; RUN: -march=arm64 | FileCheck %s |
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3 | |
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4 | define i64 @ror_i64(i64 %in) { |
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5 | ; CHECK-LABEL: ror_i64: |
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6 | %left = shl i64 %in, 19 |
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7 | %right = lshr i64 %in, 45 |
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8 | %val5 = or i64 %left, %right |
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9 | ; CHECK: ror {{x[0-9]+}}, x0, #45 |
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10 | ret i64 %val5 |
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11 | } |
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12 | |
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13 | define i32 @ror_i32(i32 %in) { |
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14 | ; CHECK-LABEL: ror_i32: |
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15 | %left = shl i32 %in, 9 |
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16 | %right = lshr i32 %in, 23 |
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17 | %val5 = or i32 %left, %right |
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18 | ; CHECK: ror {{w[0-9]+}}, w0, #23 |
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19 | ret i32 %val5 |
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20 | } |
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21 | |
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22 | define i32 @extr_i32(i32 %lhs, i32 %rhs) { |
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23 | ; CHECK-LABEL: extr_i32: |
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24 | %left = shl i32 %lhs, 6 |
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25 | %right = lshr i32 %rhs, 26 |
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26 | %val = or i32 %left, %right |
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27 | ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use |
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28 | ; something other than w0 and w1. |
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29 | ; CHECK: extr {{w[0-9]+}}, w0, w1, #26 |
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30 | |
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31 | ret i32 %val |
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32 | } |
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33 | |
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34 | define i64 @extr_i64(i64 %lhs, i64 %rhs) { |
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35 | ; CHECK-LABEL: extr_i64: |
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36 | %right = lshr i64 %rhs, 40 |
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37 | %left = shl i64 %lhs, 24 |
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38 | %val = or i64 %right, %left |
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39 | ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use |
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40 | ; something other than w0 and w1. |
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41 | ; CHECK: extr {{x[0-9]+}}, x0, x1, #40 |
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42 | |
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43 | ret i64 %val |
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44 | } |
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45 | |
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46 | ; Regression test: a bad experimental pattern crept into git which optimised |
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47 | ; this pattern to a single EXTR. |
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48 | define i32 @extr_regress(i32 %a, i32 %b) { |
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49 | ; CHECK-LABEL: extr_regress: |
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50 | |
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51 | %sh1 = shl i32 %a, 14 |
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52 | %sh2 = lshr i32 %b, 14 |
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53 | %val = or i32 %sh2, %sh1 |
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54 | ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}} |
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55 | |
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56 | ret i32 %val |
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57 | ; CHECK: ret |
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58 | } |
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