source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.5 KB
Line 
1; RUN: llc < %s
2
3; This used to assert with "Overran sorted position" in AssignTopologicalOrder
4; due to a cycle created in performPostLD1Combine.
5
6target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
7target triple = "arm64-apple-ios7.0.0"
8
9; Function Attrs: nounwind ssp
10define void @f(double* %P1) #0 {
11entry:
12  %arrayidx4 = getelementptr inbounds double, double* %P1, i64 1
13  %0 = load double, double* %arrayidx4, align 8, !tbaa !1
14  %1 = load double, double* %P1, align 8, !tbaa !1
15  %2 = insertelement <2 x double> undef, double %0, i32 0
16  %3 = insertelement <2 x double> %2, double %1, i32 1
17  %4 = fsub <2 x double> zeroinitializer, %3
18  %5 = fmul <2 x double> undef, %4
19  %6 = extractelement <2 x double> %5, i32 0
20  %cmp168 = fcmp olt double %6, undef
21  br i1 %cmp168, label %if.then172, label %return
22
23if.then172:                                       ; preds = %cond.end90
24  %7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
25  br label %return
26
27return:                                           ; preds = %if.then172, %cond.end90, %entry
28  ret void
29}
30
31; Function Attrs: nounwind readnone
32declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
33
34attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
35attributes #1 = { nounwind readnone }
36
37!1 = !{!2, !2, i64 0}
38!2 = !{!"double", !3, i64 0}
39!3 = !{!"omnipotent char", !4, i64 0}
40!4 = !{!"Simple C/C++ TBAA"}
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