source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 956 bytes
Line 
1; REQUIRES: asserts
2; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
3;
4; Test for bug in misched memory dependency calculation.
5;
6; CHECK: ********** MI Scheduling **********
7; CHECK: misched_bug:BB#0 entry
8; CHECK: SU(2):   %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
9; CHECK:   Successors:
10; CHECK-NEXT:    val SU(5): Latency=4 Reg=%vreg2
11; CHECK-NEXT:    ch  SU(4): Latency=0
12; CHECK: SU(4):   STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
13; CHECK: SU(5):   %W0<def> = COPY %vreg2; GPR32:%vreg2
14; CHECK: ** ScheduleDAGMI::schedule picking next node
15define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
16entry:
17  %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
18  %val1 = load i32, i32* %ptr1_plus1, align 4
19  store i32 0, i32* %ptr1, align 4
20  store i32 0, i32* %ptr2, align 4
21  ret i32 %val1
22}
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