source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-promote-const.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; Disable machine cse to stress the different path of the algorithm.
2; Otherwise, we always fall in the simple case, i.e., only one definition.
3; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s
4; The REGULAR run just checks that the inputs passed to promote const expose
5; the appropriate patterns.
6; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -aarch64-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s
7
8%struct.uint8x16x4_t = type { [4 x <16 x i8>] }
9
10; Constant is a structure
11define %struct.uint8x16x4_t @test1() {
12; PROMOTED-LABEL: test1:
13; Promote constant has created a big constant for the whole structure
14; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst@PAGE
15; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst@PAGEOFF
16; Destination registers are defined by the ABI
17; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]]
18; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32]
19; PROMOTED-NEXT: ret
20
21; REGULAR-LABEL: test1:
22; Regular access is quite bad, it performs 4 loads, one for each chunk of
23; the structure
24; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
25; Destination registers are defined by the ABI
26; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
27; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
28; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
29; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
30; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF]
31; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
32; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF]
33; REGULAR-NEXT: ret
34entry:
35  ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] }
36}
37
38; Two different uses of the same constant in the same basic block
39define <16 x i8> @test2(<16 x i8> %arg) {
40entry:
41; PROMOTED-LABEL: test2:
42; In stress mode, constant vector are promoted
43; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst.[0-9]+]]@PAGE
44; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
45; Destination register is defined by ABI
46; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
47; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
48; PROMOTED-NEXT: ret
49
50; REGULAR-LABEL: test2:
51; Regular access is strickly the same as promoted access.
52; The difference is that the address (and thus the space in memory) is not
53; shared between constants
54; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
55; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
56; Destination register is defined by ABI
57; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
58; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
59; REGULAR-NEXT: ret
60  %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
61  %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
62  %add.i9 = add <16 x i8> %add.i, %mul.i
63  ret <16 x i8> %add.i9
64}
65
66; Two different uses of the same constant in two different basic blocks,
67; one dominates the other
68define <16 x i8> @test3(<16 x i8> %arg, i32 %path) {
69; PROMOTED-LABEL: test3:
70; In stress mode, constant vector are promoted
71; Since, the constant is the same as the previous function,
72; the same address must be used
73; PROMOTED: ldr
74; PROMOTED: ldr
75; PROMOTED-NOT: ldr
76; PROMOTED: ret
77
78; REGULAR-LABEL: test3:
79; REGULAR: ldr
80; REGULAR: ldr
81; REGULAR-NOT: ldr
82; REGULAR: ret
83entry:
84  %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
85  %tobool = icmp eq i32 %path, 0
86  br i1 %tobool, label %if.else, label %if.then
87
88if.then:                                          ; preds = %entry
89  %mul.i13 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
90  br label %if.end
91
92if.else:                                          ; preds = %entry
93  %mul.i = mul <16 x i8> %add.i, <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>
94  br label %if.end
95
96if.end:                                           ; preds = %if.else, %if.then
97  %ret2.0 = phi <16 x i8> [ %mul.i13, %if.then ], [ %mul.i, %if.else ]
98  %add.i12 = add <16 x i8> %add.i, %ret2.0
99  ret <16 x i8> %add.i12
100}
101
102; Two different uses of the sane constant in two different basic blocks,
103; none dominates the other
104define <16 x i8> @test4(<16 x i8> %arg, i32 %path) {
105; PROMOTED-LABEL: test4:
106; In stress mode, constant vector are promoted
107; Since, the constant is the same as the previous function,
108; the same address must be used
109; PROMOTED: ldr
110; PROMOTED-NOT: ldr
111; PROMOTED: ret
112
113; REGULAR-LABEL: test4:
114; REGULAR: ldr
115; REGULAR-NOT: ldr
116; REGULAR: ret
117entry:
118  %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
119  %tobool = icmp eq i32 %path, 0
120  br i1 %tobool, label %if.end, label %if.then
121
122if.then:                                          ; preds = %entry
123  %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
124  br label %if.end
125
126if.end:                                           ; preds = %entry, %if.then
127  %ret.0 = phi <16 x i8> [ %mul.i, %if.then ], [ %add.i, %entry ]
128  ret <16 x i8> %ret.0
129}
130
131; Two different uses of the sane constant in two different basic blocks,
132; one is in a phi.
133define <16 x i8> @test5(<16 x i8> %arg, i32 %path) {
134; PROMOTED-LABEL: test5:
135; In stress mode, constant vector are promoted
136; Since, the constant is the same as the previous function,
137; the same address must be used
138; PROMOTED: ldr
139; PROMOTED-NOT: ldr
140; PROMOTED: ret
141
142; REGULAR-LABEL: test5:
143; REGULAR: ldr
144; REGULAR: ret
145entry:
146  %tobool = icmp eq i32 %path, 0
147  br i1 %tobool, label %if.end, label %if.then
148
149if.then:                                          ; preds = %entry
150  %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
151  %mul.i26 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
152  br label %if.end
153
154if.end:                                           ; preds = %entry, %if.then
155  %ret.0 = phi <16 x i8> [ %mul.i26, %if.then ], [ <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, %entry ]
156  %mul.i25 = mul <16 x i8> %ret.0, %ret.0
157  %mul.i24 = mul <16 x i8> %mul.i25, %mul.i25
158  %mul.i23 = mul <16 x i8> %mul.i24, %mul.i24
159  %mul.i = mul <16 x i8> %mul.i23, %mul.i23
160  ret <16 x i8> %mul.i
161}
162
163define void @accessBig(i64* %storage) {
164; PROMOTED-LABEL: accessBig:
165; PROMOTED: adrp
166; PROMOTED: ret
167  %addr = bitcast i64* %storage to <1 x i80>*
168  store <1 x i80> <i80 483673642326615442599424>, <1 x i80>* %addr
169  ret void
170}
171
172define void @asmStatement() {
173; PROMOTED-LABEL: asmStatement:
174; PROMOTED-NOT: adrp
175; PROMOTED: ret
176  call void asm sideeffect "bfxil w0, w0, $0, $1", "i,i"(i32 28, i32 4)
177  ret void
178}
179
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