source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-shifted-sext.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
2;
3; <rdar://problem/13820218>
4
5define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
6entry:
7; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
8; CHECK: add [[REG:w[0-9]+]], w0, #1
9; CHECK: sbfiz w0, [[REG]], #4, #8
10  %inc = add i8 %a, 1
11  %conv1 = sext i8 %inc to i32
12  %shl = shl nsw i32 %conv1, 4
13  %conv2 = trunc i32 %shl to i16
14  ret i16 %conv2
15}
16
17define signext i16 @extendedRightShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
18entry:
19; CHECK-LABEL: extendedRightShiftcharToshortBy4:
20; CHECK: add [[REG:w[0-9]+]], w0, #1
21; CHECK: sbfx w0, [[REG]], #4, #4
22  %inc = add i8 %a, 1
23  %conv1 = sext i8 %inc to i32
24  %shr4 = lshr i32 %conv1, 4
25  %conv2 = trunc i32 %shr4 to i16
26  ret i16 %conv2
27}
28
29define signext i16 @extendedLeftShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
30entry:
31; CHECK-LABEL: extendedLeftShiftcharToshortBy8:
32; CHECK: add [[REG:w[0-9]+]], w0, #1
33; CHECK: sbfiz w0, [[REG]], #8, #8
34  %inc = add i8 %a, 1
35  %conv1 = sext i8 %inc to i32
36  %shl = shl nsw i32 %conv1, 8
37  %conv2 = trunc i32 %shl to i16
38  ret i16 %conv2
39}
40
41define signext i16 @extendedRightShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
42entry:
43; CHECK-LABEL: extendedRightShiftcharToshortBy8:
44; CHECK: add [[REG:w[0-9]+]], w0, #1
45; CHECK: sxtb [[REG]], [[REG]]
46; CHECK: asr w0, [[REG]], #8
47  %inc = add i8 %a, 1
48  %conv1 = sext i8 %inc to i32
49  %shr4 = lshr i32 %conv1, 8
50  %conv2 = trunc i32 %shr4 to i16
51  ret i16 %conv2
52}
53
54define i32 @extendedLeftShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
55entry:
56; CHECK-LABEL: extendedLeftShiftcharTointBy4:
57; CHECK: add [[REG:w[0-9]+]], w0, #1
58; CHECK: sbfiz w0, [[REG]], #4, #8
59  %inc = add i8 %a, 1
60  %conv = sext i8 %inc to i32
61  %shl = shl nsw i32 %conv, 4
62  ret i32 %shl
63}
64
65define i32 @extendedRightShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
66entry:
67; CHECK-LABEL: extendedRightShiftcharTointBy4:
68; CHECK: add [[REG:w[0-9]+]], w0, #1
69; CHECK: sbfx w0, [[REG]], #4, #4
70  %inc = add i8 %a, 1
71  %conv = sext i8 %inc to i32
72  %shr = ashr i32 %conv, 4
73  ret i32 %shr
74}
75
76define i32 @extendedLeftShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
77entry:
78; CHECK-LABEL: extendedLeftShiftcharTointBy8:
79; CHECK: add [[REG:w[0-9]+]], w0, #1
80; CHECK: sbfiz w0, [[REG]], #8, #8
81  %inc = add i8 %a, 1
82  %conv = sext i8 %inc to i32
83  %shl = shl nsw i32 %conv, 8
84  ret i32 %shl
85}
86
87define i32 @extendedRightShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
88entry:
89; CHECK-LABEL: extendedRightShiftcharTointBy8:
90; CHECK: add [[REG:w[0-9]+]], w0, #1
91; CHECK: sxtb [[REG]], [[REG]]
92; CHECK: asr w0, [[REG]], #8
93  %inc = add i8 %a, 1
94  %conv = sext i8 %inc to i32
95  %shr = ashr i32 %conv, 8
96  ret i32 %shr
97}
98
99define i64 @extendedLeftShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
100entry:
101; CHECK-LABEL: extendedLeftShiftcharToint64By4:
102; CHECK: add w[[REG:[0-9]+]], w0, #1
103; CHECK: sbfiz x0, x[[REG]], #4, #8
104  %inc = add i8 %a, 1
105  %conv = sext i8 %inc to i64
106  %shl = shl nsw i64 %conv, 4
107  ret i64 %shl
108}
109
110define i64 @extendedRightShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
111entry:
112; CHECK-LABEL: extendedRightShiftcharToint64By4:
113; CHECK: add w[[REG:[0-9]+]], w0, #1
114; CHECK: sbfx x0, x[[REG]], #4, #4
115  %inc = add i8 %a, 1
116  %conv = sext i8 %inc to i64
117  %shr = ashr i64 %conv, 4
118  ret i64 %shr
119}
120
121define i64 @extendedLeftShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
122entry:
123; CHECK-LABEL: extendedLeftShiftcharToint64By8:
124; CHECK: add w[[REG:[0-9]+]], w0, #1
125; CHECK: sbfiz x0, x[[REG]], #8, #8
126  %inc = add i8 %a, 1
127  %conv = sext i8 %inc to i64
128  %shl = shl nsw i64 %conv, 8
129  ret i64 %shl
130}
131
132define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
133entry:
134; CHECK-LABEL: extendedRightShiftcharToint64By8:
135; CHECK: add w[[REG:[0-9]+]], w0, #1
136; CHECK: sxtb x[[REG]], w[[REG]]
137; CHECK: asr x0, x[[REG]], #8
138  %inc = add i8 %a, 1
139  %conv = sext i8 %inc to i64
140  %shr = ashr i64 %conv, 8
141  ret i64 %shr
142}
143
144define i32 @extendedLeftShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
145entry:
146; CHECK-LABEL: extendedLeftShiftshortTointBy4:
147; CHECK: add [[REG:w[0-9]+]], w0, #1
148; CHECK: sbfiz w0, [[REG]], #4, #16
149  %inc = add i16 %a, 1
150  %conv = sext i16 %inc to i32
151  %shl = shl nsw i32 %conv, 4
152  ret i32 %shl
153}
154
155define i32 @extendedRightShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
156entry:
157; CHECK-LABEL: extendedRightShiftshortTointBy4:
158; CHECK: add [[REG:w[0-9]+]], w0, #1
159; CHECK: sbfx w0, [[REG]], #4, #12
160  %inc = add i16 %a, 1
161  %conv = sext i16 %inc to i32
162  %shr = ashr i32 %conv, 4
163  ret i32 %shr
164}
165
166define i32 @extendedLeftShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
167entry:
168; CHECK-LABEL: extendedLeftShiftshortTointBy16:
169; CHECK: lsl [[REG:w[0-9]+]], w0, #16
170; CHECK: add w0, [[REG]], #16, lsl #12
171  %inc = add i16 %a, 1
172  %conv2 = zext i16 %inc to i32
173  %shl = shl nuw i32 %conv2, 16
174  ret i32 %shl
175}
176
177define i32 @extendedRightShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
178entry:
179; CHECK-LABEL: extendedRightShiftshortTointBy16:
180; CHECK: add [[REG:w[0-9]+]], w0, #1
181; CHECK: sxth [[REG]], [[REG]]
182; CHECK: asr w0, [[REG]], #16
183  %inc = add i16 %a, 1
184  %conv = sext i16 %inc to i32
185  %shr = ashr i32 %conv, 16
186  ret i32 %shr
187}
188
189define i64 @extendedLeftShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
190entry:
191; CHECK-LABEL: extendedLeftShiftshortToint64By4:
192; CHECK: add w[[REG:[0-9]+]], w0, #1
193; CHECK: sbfiz x0, x[[REG]], #4, #16
194  %inc = add i16 %a, 1
195  %conv = sext i16 %inc to i64
196  %shl = shl nsw i64 %conv, 4
197  ret i64 %shl
198}
199
200define i64 @extendedRightShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
201entry:
202; CHECK-LABEL: extendedRightShiftshortToint64By4:
203; CHECK: add w[[REG:[0-9]+]], w0, #1
204; CHECK: sbfx x0, x[[REG]], #4, #12
205  %inc = add i16 %a, 1
206  %conv = sext i16 %inc to i64
207  %shr = ashr i64 %conv, 4
208  ret i64 %shr
209}
210
211define i64 @extendedLeftShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
212entry:
213; CHECK-LABEL: extendedLeftShiftshortToint64By16:
214; CHECK: add w[[REG:[0-9]+]], w0, #1
215; CHECK: sbfiz x0, x[[REG]], #16, #16
216  %inc = add i16 %a, 1
217  %conv = sext i16 %inc to i64
218  %shl = shl nsw i64 %conv, 16
219  ret i64 %shl
220}
221
222define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
223entry:
224; CHECK-LABEL: extendedRightShiftshortToint64By16:
225; CHECK: add w[[REG:[0-9]+]], w0, #1
226; CHECK: sxth x[[REG]], w[[REG]]
227; CHECK: asr x0, x[[REG]], #16
228  %inc = add i16 %a, 1
229  %conv = sext i16 %inc to i64
230  %shr = ashr i64 %conv, 16
231  ret i64 %shr
232}
233
234define i64 @extendedLeftShiftintToint64By4(i32 %a) nounwind readnone ssp {
235entry:
236; CHECK-LABEL: extendedLeftShiftintToint64By4:
237; CHECK: add w[[REG:[0-9]+]], w0, #1
238; CHECK: sbfiz x0, x[[REG]], #4, #32
239  %inc = add nsw i32 %a, 1
240  %conv = sext i32 %inc to i64
241  %shl = shl nsw i64 %conv, 4
242  ret i64 %shl
243}
244
245define i64 @extendedRightShiftintToint64By4(i32 %a) nounwind readnone ssp {
246entry:
247; CHECK-LABEL: extendedRightShiftintToint64By4:
248; CHECK: add w[[REG:[0-9]+]], w0, #1
249; CHECK: sbfx x0, x[[REG]], #4, #28
250  %inc = add nsw i32 %a, 1
251  %conv = sext i32 %inc to i64
252  %shr = ashr i64 %conv, 4
253  ret i64 %shr
254}
255
256define i64 @extendedLeftShiftintToint64By32(i32 %a) nounwind readnone ssp {
257entry:
258; CHECK-LABEL: extendedLeftShiftintToint64By32:
259; CHECK: add w[[REG:[0-9]+]], w0, #1
260; CHECK: lsl x0, x[[REG]], #32
261  %inc = add nsw i32 %a, 1
262  %conv2 = zext i32 %inc to i64
263  %shl = shl nuw i64 %conv2, 32
264  ret i64 %shl
265}
266
267define i64 @extendedRightShiftintToint64By32(i32 %a) nounwind readnone ssp {
268entry:
269; CHECK-LABEL: extendedRightShiftintToint64By32:
270; CHECK: add w[[REG:[0-9]+]], w0, #1
271; CHECK: sxtw x[[REG]], w[[REG]]
272; CHECK: asr x0, x[[REG]], #32
273  %inc = add nsw i32 %a, 1
274  %conv = sext i32 %inc to i64
275  %shr = ashr i64 %conv, 32
276  ret i64 %shr
277}
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