source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-simd-scalar-to-vector.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 957 bytes
Line 
1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
2; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
3
4define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
5; CHECK: uaddlv.16b h0, v0
6; CHECK: rshrn.8b v0, v0, #4
7; CHECK: dup.16b v0, v0[0]
8; CHECK: ret
9
10; CHECK-FAST: uaddlv.16b
11; CHECK-FAST: rshrn.8b
12; CHECK-FAST: dup.16b
13  %tmp = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
14  %tmp1 = trunc i32 %tmp to i16
15  %tmp2 = insertelement <8 x i16> undef, i16 %tmp1, i32 0
16  %tmp3 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp2, i32 4)
17  %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <16 x i32> zeroinitializer
18  ret <16 x i8> %tmp4
19}
20
21declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
22declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>) nounwind readnone
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