source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-vclz.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 3.5 KB
Line 
1; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s
2
3define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
4  ; CHECK-LABEL: test_vclz_u8:
5  ; CHECK: clz.8b v0, v0
6  ; CHECK-NEXT: ret
7  %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
8  ret <8 x i8> %vclz.i
9}
10
11define <8 x i8> @test_vclz_s8(<8 x i8> %a) nounwind readnone ssp {
12  ; CHECK-LABEL: test_vclz_s8:
13  ; CHECK: clz.8b v0, v0
14  ; CHECK-NEXT: ret
15  %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
16  ret <8 x i8> %vclz.i
17}
18
19define <4 x i16> @test_vclz_u16(<4 x i16> %a) nounwind readnone ssp {
20  ; CHECK-LABEL: test_vclz_u16:
21  ; CHECK: clz.4h v0, v0
22  ; CHECK-NEXT: ret
23  %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
24  ret <4 x i16> %vclz1.i
25}
26
27define <4 x i16> @test_vclz_s16(<4 x i16> %a) nounwind readnone ssp {
28  ; CHECK-LABEL: test_vclz_s16:
29  ; CHECK: clz.4h v0, v0
30  ; CHECK-NEXT: ret
31  %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
32  ret <4 x i16> %vclz1.i
33}
34
35define <2 x i32> @test_vclz_u32(<2 x i32> %a) nounwind readnone ssp {
36  ; CHECK-LABEL: test_vclz_u32:
37  ; CHECK: clz.2s v0, v0
38  ; CHECK-NEXT: ret
39  %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
40  ret <2 x i32> %vclz1.i
41}
42
43define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp {
44  ; CHECK-LABEL: test_vclz_s32:
45  ; CHECK: clz.2s v0, v0
46  ; CHECK-NEXT: ret
47  %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
48  ret <2 x i32> %vclz1.i
49}
50
51define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
52  ; CHECK-LABEL: test_vclzq_u8:
53  ; CHECK: clz.16b v0, v0
54  ; CHECK-NEXT: ret
55  %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
56  ret <16 x i8> %vclz.i
57}
58
59define <16 x i8> @test_vclzq_s8(<16 x i8> %a) nounwind readnone ssp {
60  ; CHECK-LABEL: test_vclzq_s8:
61  ; CHECK: clz.16b v0, v0
62  ; CHECK-NEXT: ret
63  %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
64  ret <16 x i8> %vclz.i
65}
66
67define <8 x i16> @test_vclzq_u16(<8 x i16> %a) nounwind readnone ssp {
68  ; CHECK-LABEL: test_vclzq_u16:
69  ; CHECK: clz.8h v0, v0
70  ; CHECK-NEXT: ret
71  %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
72  ret <8 x i16> %vclz1.i
73}
74
75define <8 x i16> @test_vclzq_s16(<8 x i16> %a) nounwind readnone ssp {
76  ; CHECK-LABEL: test_vclzq_s16:
77  ; CHECK: clz.8h v0, v0
78  ; CHECK-NEXT: ret
79  %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
80  ret <8 x i16> %vclz1.i
81}
82
83define <4 x i32> @test_vclzq_u32(<4 x i32> %a) nounwind readnone ssp {
84  ; CHECK-LABEL: test_vclzq_u32:
85  ; CHECK: clz.4s v0, v0
86  ; CHECK-NEXT: ret
87  %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
88  ret <4 x i32> %vclz1.i
89}
90
91define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp {
92  ; CHECK-LABEL: test_vclzq_s32:
93  ; CHECK: clz.4s v0, v0
94  ; CHECK-NEXT: ret
95  %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
96  ret <4 x i32> %vclz1.i
97}
98
99declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
100
101declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
102
103declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
104
105declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
106
107declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
108
109declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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