source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-vhsub.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 4.6 KB
Line 
1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
2
3define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4;CHECK-LABEL: shsub8b:
5;CHECK: shsub.8b
6        %tmp1 = load <8 x i8>, <8 x i8>* %A
7        %tmp2 = load <8 x i8>, <8 x i8>* %B
8        %tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9        ret <8 x i8> %tmp3
10}
11
12define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
13;CHECK-LABEL: shsub16b:
14;CHECK: shsub.16b
15        %tmp1 = load <16 x i8>, <16 x i8>* %A
16        %tmp2 = load <16 x i8>, <16 x i8>* %B
17        %tmp3 = call <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
18        ret <16 x i8> %tmp3
19}
20
21define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
22;CHECK-LABEL: shsub4h:
23;CHECK: shsub.4h
24        %tmp1 = load <4 x i16>, <4 x i16>* %A
25        %tmp2 = load <4 x i16>, <4 x i16>* %B
26        %tmp3 = call <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
27        ret <4 x i16> %tmp3
28}
29
30define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
31;CHECK-LABEL: shsub8h:
32;CHECK: shsub.8h
33        %tmp1 = load <8 x i16>, <8 x i16>* %A
34        %tmp2 = load <8 x i16>, <8 x i16>* %B
35        %tmp3 = call <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
36        ret <8 x i16> %tmp3
37}
38
39define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
40;CHECK-LABEL: shsub2s:
41;CHECK: shsub.2s
42        %tmp1 = load <2 x i32>, <2 x i32>* %A
43        %tmp2 = load <2 x i32>, <2 x i32>* %B
44        %tmp3 = call <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
45        ret <2 x i32> %tmp3
46}
47
48define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
49;CHECK-LABEL: shsub4s:
50;CHECK: shsub.4s
51        %tmp1 = load <4 x i32>, <4 x i32>* %A
52        %tmp2 = load <4 x i32>, <4 x i32>* %B
53        %tmp3 = call <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
54        ret <4 x i32> %tmp3
55}
56
57define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
58;CHECK-LABEL: uhsub8b:
59;CHECK: uhsub.8b
60        %tmp1 = load <8 x i8>, <8 x i8>* %A
61        %tmp2 = load <8 x i8>, <8 x i8>* %B
62        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
63        ret <8 x i8> %tmp3
64}
65
66define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
67;CHECK-LABEL: uhsub16b:
68;CHECK: uhsub.16b
69        %tmp1 = load <16 x i8>, <16 x i8>* %A
70        %tmp2 = load <16 x i8>, <16 x i8>* %B
71        %tmp3 = call <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
72        ret <16 x i8> %tmp3
73}
74
75define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
76;CHECK-LABEL: uhsub4h:
77;CHECK: uhsub.4h
78        %tmp1 = load <4 x i16>, <4 x i16>* %A
79        %tmp2 = load <4 x i16>, <4 x i16>* %B
80        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
81        ret <4 x i16> %tmp3
82}
83
84define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
85;CHECK-LABEL: uhsub8h:
86;CHECK: uhsub.8h
87        %tmp1 = load <8 x i16>, <8 x i16>* %A
88        %tmp2 = load <8 x i16>, <8 x i16>* %B
89        %tmp3 = call <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
90        ret <8 x i16> %tmp3
91}
92
93define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
94;CHECK-LABEL: uhsub2s:
95;CHECK: uhsub.2s
96        %tmp1 = load <2 x i32>, <2 x i32>* %A
97        %tmp2 = load <2 x i32>, <2 x i32>* %B
98        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
99        ret <2 x i32> %tmp3
100}
101
102define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
103;CHECK-LABEL: uhsub4s:
104;CHECK: uhsub.4s
105        %tmp1 = load <4 x i32>, <4 x i32>* %A
106        %tmp2 = load <4 x i32>, <4 x i32>* %B
107        %tmp3 = call <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
108        ret <4 x i32> %tmp3
109}
110
111declare <8 x i8>  @llvm.aarch64.neon.shsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
112declare <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
113declare <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
114
115declare <8 x i8>  @llvm.aarch64.neon.uhsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
116declare <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
117declare <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
118
119declare <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
120declare <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
121declare <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
122
123declare <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
124declare <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
125declare <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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