source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-vmovn.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 8.0 KB
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1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
2
3define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
4;CHECK-LABEL: xtn8b:
5;CHECK-NOT: ld1
6;CHECK: xtn.8b v0, v0
7;CHECK-NEXT: ret
8  %tmp3 = trunc <8 x i16> %A to <8 x i8>
9        ret <8 x i8> %tmp3
10}
11
12define <4 x i16> @xtn4h(<4 x i32> %A) nounwind {
13;CHECK-LABEL: xtn4h:
14;CHECK-NOT: ld1
15;CHECK: xtn.4h v0, v0
16;CHECK-NEXT: ret
17  %tmp3 = trunc <4 x i32> %A to <4 x i16>
18        ret <4 x i16> %tmp3
19}
20
21define <2 x i32> @xtn2s(<2 x i64> %A) nounwind {
22;CHECK-LABEL: xtn2s:
23;CHECK-NOT: ld1
24;CHECK: xtn.2s v0, v0
25;CHECK-NEXT: ret
26  %tmp3 = trunc <2 x i64> %A to <2 x i32>
27        ret <2 x i32> %tmp3
28}
29
30define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
31;CHECK-LABEL: xtn2_16b:
32;CHECK-NOT: ld1
33;CHECK: xtn2.16b v0, v1
34;CHECK-NEXT: ret
35        %tmp3 = trunc <8 x i16> %A to <8 x i8>
36        %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
37        ret <16 x i8> %res
38}
39
40define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
41;CHECK-LABEL: xtn2_8h:
42;CHECK-NOT: ld1
43;CHECK: xtn2.8h v0, v1
44;CHECK-NEXT: ret
45        %tmp3 = trunc <4 x i32> %A to <4 x i16>
46        %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
47        ret <8 x i16> %res
48}
49
50define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
51;CHECK-LABEL: xtn2_4s:
52;CHECK-NOT: ld1
53;CHECK: xtn2.4s v0, v1
54;CHECK-NEXT: ret
55        %tmp3 = trunc <2 x i64> %A to <2 x i32>
56        %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
57        ret <4 x i32> %res
58}
59
60define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind {
61;CHECK-LABEL: sqxtn8b:
62;CHECK-NOT: ld1
63;CHECK: sqxtn.8b v0, v0
64;CHECK-NEXT: ret
65        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)
66        ret <8 x i8> %tmp3
67}
68
69define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind {
70;CHECK-LABEL: sqxtn4h:
71;CHECK-NOT: ld1
72;CHECK: sqxtn.4h v0, v0
73;CHECK-NEXT: ret
74        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)
75        ret <4 x i16> %tmp3
76}
77
78define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind {
79;CHECK-LABEL: sqxtn2s:
80;CHECK-NOT: ld1
81;CHECK: sqxtn.2s v0, v0
82;CHECK-NEXT: ret
83        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)
84        ret <2 x i32> %tmp3
85}
86
87define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
88;CHECK-LABEL: sqxtn2_16b:
89;CHECK-NOT: ld1
90;CHECK: sqxtn2.16b v0, v1
91;CHECK-NEXT: ret
92        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)
93        %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
94        ret <16 x i8> %res
95}
96
97define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
98;CHECK-LABEL: sqxtn2_8h:
99;CHECK-NOT: ld1
100;CHECK: sqxtn2.8h v0, v1
101;CHECK-NEXT: ret
102        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)
103        %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
104        ret <8 x i16> %res
105}
106
107define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
108;CHECK-LABEL: sqxtn2_4s:
109;CHECK-NOT: ld1
110;CHECK: sqxtn2.4s v0, v1
111;CHECK-NEXT: ret
112        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)
113        %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
114        ret <4 x i32> %res
115}
116
117declare <8 x i8>  @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone
118declare <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone
119declare <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone
120
121define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind {
122;CHECK-LABEL: uqxtn8b:
123;CHECK-NOT: ld1
124;CHECK: uqxtn.8b v0, v0
125;CHECK-NEXT: ret
126        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)
127        ret <8 x i8> %tmp3
128}
129
130define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind {
131;CHECK-LABEL: uqxtn4h:
132;CHECK-NOT: ld1
133;CHECK: uqxtn.4h v0, v0
134;CHECK-NEXT: ret
135        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)
136        ret <4 x i16> %tmp3
137}
138
139define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind {
140;CHECK-LABEL: uqxtn2s:
141;CHECK-NOT: ld1
142;CHECK: uqxtn.2s v0, v0
143;CHECK-NEXT: ret
144        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)
145        ret <2 x i32> %tmp3
146}
147
148define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
149;CHECK-LABEL: uqxtn2_16b:
150;CHECK-NOT: ld1
151;CHECK: uqxtn2.16b v0, v1
152;CHECK-NEXT: ret
153        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)
154        %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
155        ret <16 x i8> %res
156}
157
158define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
159;CHECK-LABEL: uqxtn2_8h:
160;CHECK-NOT: ld1
161;CHECK: uqxtn2.8h v0, v1
162;CHECK-NEXT: ret
163        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)
164        %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
165        ret <8 x i16> %res
166}
167
168define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
169;CHECK-LABEL: uqxtn2_4s:
170;CHECK-NOT: ld1
171;CHECK: uqxtn2.4s v0, v1
172;CHECK-NEXT: ret
173        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)
174        %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
175        ret <4 x i32> %res
176}
177
178declare <8 x i8>  @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone
179declare <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone
180declare <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone
181
182define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind {
183;CHECK-LABEL: sqxtun8b:
184;CHECK-NOT: ld1
185;CHECK: sqxtun.8b v0, v0
186;CHECK-NEXT: ret
187        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)
188        ret <8 x i8> %tmp3
189}
190
191define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind {
192;CHECK-LABEL: sqxtun4h:
193;CHECK-NOT: ld1
194;CHECK: sqxtun.4h v0, v0
195;CHECK-NEXT: ret
196        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)
197        ret <4 x i16> %tmp3
198}
199
200define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind {
201;CHECK-LABEL: sqxtun2s:
202;CHECK-NOT: ld1
203;CHECK: sqxtun.2s v0, v0
204;CHECK-NEXT: ret
205        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)
206        ret <2 x i32> %tmp3
207}
208
209define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
210;CHECK-LABEL: sqxtun2_16b:
211;CHECK-NOT: ld1
212;CHECK: sqxtun2.16b v0, v1
213;CHECK-NEXT: ret
214        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)
215        %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
216        ret <16 x i8> %res
217}
218
219define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
220;CHECK-LABEL: sqxtun2_8h:
221;CHECK-NOT: ld1
222;CHECK: sqxtun2.8h v0, v1
223;CHECK-NEXT: ret
224        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)
225        %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
226        ret <8 x i16> %res
227}
228
229define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
230;CHECK-LABEL: sqxtun2_4s:
231;CHECK-NOT: ld1
232;CHECK: sqxtun2.4s v0, v1
233;CHECK-NEXT: ret
234        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)
235        %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
236        ret <4 x i32> %res
237}
238
239declare <8 x i8>  @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone
240declare <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone
241declare <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone
242
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