source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/arm64-vqsub.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 5.5 KB
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1; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
2
3define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4;CHECK-LABEL: sqsub8b:
5;CHECK: sqsub.8b
6        %tmp1 = load <8 x i8>, <8 x i8>* %A
7        %tmp2 = load <8 x i8>, <8 x i8>* %B
8        %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
9        ret <8 x i8> %tmp3
10}
11
12define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13;CHECK-LABEL: sqsub4h:
14;CHECK: sqsub.4h
15        %tmp1 = load <4 x i16>, <4 x i16>* %A
16        %tmp2 = load <4 x i16>, <4 x i16>* %B
17        %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
18        ret <4 x i16> %tmp3
19}
20
21define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
22;CHECK-LABEL: sqsub2s:
23;CHECK: sqsub.2s
24        %tmp1 = load <2 x i32>, <2 x i32>* %A
25        %tmp2 = load <2 x i32>, <2 x i32>* %B
26        %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
27        ret <2 x i32> %tmp3
28}
29
30define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
31;CHECK-LABEL: uqsub8b:
32;CHECK: uqsub.8b
33        %tmp1 = load <8 x i8>, <8 x i8>* %A
34        %tmp2 = load <8 x i8>, <8 x i8>* %B
35        %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
36        ret <8 x i8> %tmp3
37}
38
39define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
40;CHECK-LABEL: uqsub4h:
41;CHECK: uqsub.4h
42        %tmp1 = load <4 x i16>, <4 x i16>* %A
43        %tmp2 = load <4 x i16>, <4 x i16>* %B
44        %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
45        ret <4 x i16> %tmp3
46}
47
48define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
49;CHECK-LABEL: uqsub2s:
50;CHECK: uqsub.2s
51        %tmp1 = load <2 x i32>, <2 x i32>* %A
52        %tmp2 = load <2 x i32>, <2 x i32>* %B
53        %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
54        ret <2 x i32> %tmp3
55}
56
57define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
58;CHECK-LABEL: sqsub16b:
59;CHECK: sqsub.16b
60        %tmp1 = load <16 x i8>, <16 x i8>* %A
61        %tmp2 = load <16 x i8>, <16 x i8>* %B
62        %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
63        ret <16 x i8> %tmp3
64}
65
66define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
67;CHECK-LABEL: sqsub8h:
68;CHECK: sqsub.8h
69        %tmp1 = load <8 x i16>, <8 x i16>* %A
70        %tmp2 = load <8 x i16>, <8 x i16>* %B
71        %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
72        ret <8 x i16> %tmp3
73}
74
75define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
76;CHECK-LABEL: sqsub4s:
77;CHECK: sqsub.4s
78        %tmp1 = load <4 x i32>, <4 x i32>* %A
79        %tmp2 = load <4 x i32>, <4 x i32>* %B
80        %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
81        ret <4 x i32> %tmp3
82}
83
84define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
85;CHECK-LABEL: sqsub2d:
86;CHECK: sqsub.2d
87        %tmp1 = load <2 x i64>, <2 x i64>* %A
88        %tmp2 = load <2 x i64>, <2 x i64>* %B
89        %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
90        ret <2 x i64> %tmp3
91}
92
93define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
94;CHECK-LABEL: uqsub16b:
95;CHECK: uqsub.16b
96        %tmp1 = load <16 x i8>, <16 x i8>* %A
97        %tmp2 = load <16 x i8>, <16 x i8>* %B
98        %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
99        ret <16 x i8> %tmp3
100}
101
102define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
103;CHECK-LABEL: uqsub8h:
104;CHECK: uqsub.8h
105        %tmp1 = load <8 x i16>, <8 x i16>* %A
106        %tmp2 = load <8 x i16>, <8 x i16>* %B
107        %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
108        ret <8 x i16> %tmp3
109}
110
111define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
112;CHECK-LABEL: uqsub4s:
113;CHECK: uqsub.4s
114        %tmp1 = load <4 x i32>, <4 x i32>* %A
115        %tmp2 = load <4 x i32>, <4 x i32>* %B
116        %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
117        ret <4 x i32> %tmp3
118}
119
120define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
121;CHECK-LABEL: uqsub2d:
122;CHECK: uqsub.2d
123        %tmp1 = load <2 x i64>, <2 x i64>* %A
124        %tmp2 = load <2 x i64>, <2 x i64>* %B
125        %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
126        ret <2 x i64> %tmp3
127}
128
129declare <8 x i8>  @llvm.aarch64.neon.sqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
130declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
131declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
132declare <1 x i64> @llvm.aarch64.neon.sqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
133
134declare <8 x i8>  @llvm.aarch64.neon.uqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
135declare <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
136declare <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
137declare <1 x i64> @llvm.aarch64.neon.uqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
138
139declare <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
140declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
141declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
142declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
143
144declare <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
145declare <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
146declare <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
147declare <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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