source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/extract.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.5 KB
Line 
1; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
2
3define i64 @ror_i64(i64 %in) {
4; CHECK-LABEL: ror_i64:
5    %left = shl i64 %in, 19
6    %right = lshr i64 %in, 45
7    %val5 = or i64 %left, %right
8; CHECK: ror {{x[0-9]+}}, x0, #45
9    ret i64 %val5
10}
11
12define i32 @ror_i32(i32 %in) {
13; CHECK-LABEL: ror_i32:
14    %left = shl i32 %in, 9
15    %right = lshr i32 %in, 23
16    %val5 = or i32 %left, %right
17; CHECK: ror {{w[0-9]+}}, w0, #23
18    ret i32 %val5
19}
20
21define i32 @extr_i32(i32 %lhs, i32 %rhs) {
22; CHECK-LABEL: extr_i32:
23  %left = shl i32 %lhs, 6
24  %right = lshr i32 %rhs, 26
25  %val = or i32 %left, %right
26  ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
27  ; something other than w0 and w1.
28; CHECK: extr {{w[0-9]+}}, w0, w1, #26
29
30  ret i32 %val
31}
32
33define i64 @extr_i64(i64 %lhs, i64 %rhs) {
34; CHECK-LABEL: extr_i64:
35  %right = lshr i64 %rhs, 40
36  %left = shl i64 %lhs, 24
37  %val = or i64 %right, %left
38  ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
39  ; something other than w0 and w1.
40; CHECK: extr {{x[0-9]+}}, x0, x1, #40
41
42  ret i64 %val
43}
44
45; Regression test: a bad experimental pattern crept into git which optimised
46; this pattern to a single EXTR.
47define i32 @extr_regress(i32 %a, i32 %b) {
48; CHECK-LABEL: extr_regress:
49
50    %sh1 = shl i32 %a, 14
51    %sh2 = lshr i32 %b, 14
52    %val = or i32 %sh2, %sh1
53; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
54
55    ret i32 %val
56; CHECK: ret
57}
Note: See TracBrowser for help on using the repository browser.