source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/fast-isel-cmp-vec.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs \
2; RUN:   -aarch64-atomic-cfg-tidy=0 -disable-cgp -disable-branch-fold \
3; RUN:   < %s | FileCheck %s
4
5;
6; Verify that we don't mess up vector comparisons in fast-isel.
7;
8
9define <2 x i32> @icmp_v2i32(<2 x i32> %a) {
10; CHECK-LABEL: icmp_v2i32:
11; CHECK:      ; BB#0:
12; CHECK-NEXT:  cmeq.2s [[CMP:v[0-9]+]], v0, #0
13; CHECK-NEXT: ; BB#1:
14; CHECK-NEXT:  movi.2s [[MASK:v[0-9]+]], #0x1
15; CHECK-NEXT:  and.8b v0, [[CMP]], [[MASK]]
16; CHECK-NEXT:  ret
17  %c = icmp eq <2 x i32> %a, zeroinitializer
18  br label %bb2
19bb2:
20  %z = zext <2 x i1> %c to <2 x i32>
21  ret <2 x i32> %z
22}
23
24define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
25; CHECK-LABEL: icmp_constfold_v2i32:
26; CHECK:      ; BB#0:
27; CHECK-NEXT:  movi d[[CMP:[0-9]+]], #0xffffffffffffffff
28; CHECK-NEXT: ; BB#1:
29; CHECK-NEXT:  movi.2s [[MASK:v[0-9]+]], #0x1
30; CHECK-NEXT:  and.8b v0, v[[CMP]], [[MASK]]
31; CHECK-NEXT:  ret
32  %1 = icmp eq <2 x i32> %a, %a
33  br label %bb2
34bb2:
35  %2 = zext <2 x i1> %1 to <2 x i32>
36  ret <2 x i32> %2
37}
38
39define <4 x i32> @icmp_v4i32(<4 x i32> %a) {
40; CHECK-LABEL: icmp_v4i32:
41; CHECK:      ; BB#0:
42; CHECK-NEXT:  cmeq.4s [[CMP:v[0-9]+]], v0, #0
43; CHECK-NEXT:  xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]]
44; CHECK-NEXT: ; BB#1:
45; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #0x1
46; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
47; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
48; CHECK-NEXT:  ret
49  %c = icmp eq <4 x i32> %a, zeroinitializer
50  br label %bb2
51bb2:
52  %z = zext <4 x i1> %c to <4 x i32>
53  ret <4 x i32> %z
54}
55
56define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
57; CHECK-LABEL: icmp_constfold_v4i32:
58; CHECK:      ; BB#0:
59; CHECK-NEXT:  movi d[[CMP:[0-9]+]], #0xffffffffffffffff
60; CHECK-NEXT: ; BB#1:
61; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #0x1
62; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
63; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
64; CHECK-NEXT:  ret
65  %1 = icmp eq <4 x i32> %a, %a
66  br label %bb2
67bb2:
68  %2 = zext <4 x i1> %1 to <4 x i32>
69  ret <4 x i32> %2
70}
71
72define <16 x i8> @icmp_v16i8(<16 x i8> %a) {
73; CHECK-LABEL: icmp_v16i8:
74; CHECK:      ; BB#0:
75; CHECK-NEXT:  cmeq.16b [[CMP:v[0-9]+]], v0, #0
76; CHECK-NEXT: ; BB#1:
77; CHECK-NEXT:  movi.16b [[MASK:v[0-9]+]], #0x1
78; CHECK-NEXT:  and.16b v0, [[CMP]], [[MASK]]
79; CHECK-NEXT:  ret
80  %c = icmp eq <16 x i8> %a, zeroinitializer
81  br label %bb2
82bb2:
83  %z = zext <16 x i1> %c to <16 x i8>
84  ret <16 x i8> %z
85}
86
87define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
88; CHECK-LABEL: icmp_constfold_v16i8:
89; CHECK:      ; BB#0:
90; CHECK-NEXT:  movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff
91; CHECK-NEXT: ; BB#1:
92; CHECK-NEXT:  movi.16b [[MASK:v[0-9]+]], #0x1
93; CHECK-NEXT:  and.16b v0, [[CMP]], [[MASK]]
94; CHECK-NEXT:  ret
95  %1 = icmp eq <16 x i8> %a, %a
96  br label %bb2
97bb2:
98  %2 = zext <16 x i1> %1 to <16 x i8>
99  ret <16 x i8> %2
100}
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