source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/fast-isel-logic-op.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0                    -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
3
4; AND
5define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
6; CHECK-LABEL: and_rr_i1
7; CHECK:       and [[REG:w[0-9]+]], w0, w1
8  %1 = and i1 %a, %b
9  ret i1 %1
10}
11
12define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {
13; CHECK-LABEL: and_rr_i8
14; CHECK:       and [[REG:w[0-9]+]], w0, w1
15; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xff
16  %1 = and i8 %a, %b
17  ret i8 %1
18}
19
20define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {
21; CHECK-LABEL: and_rr_i16
22; CHECK:       and [[REG:w[0-9]+]], w0, w1
23; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xffff
24  %1 = and i16 %a, %b
25  ret i16 %1
26}
27
28define i32 @and_rr_i32(i32 %a, i32 %b) {
29; CHECK-LABEL: and_rr_i32
30; CHECK:       and w0, w0, w1
31  %1 = and i32 %a, %b
32  ret i32 %1
33}
34
35define i64 @and_rr_i64(i64 %a, i64 %b) {
36; CHECK-LABEL: and_rr_i64
37; CHECK:       and x0, x0, x1
38  %1 = and i64 %a, %b
39  ret i64 %1
40}
41
42define zeroext i1 @and_ri_i1(i1 signext %a) {
43; CHECK-LABEL: and_ri_i1
44; CHECK:       and {{w[0-9]+}}, w0, #0x1
45  %1 = and i1 %a, 1
46  ret i1 %1
47}
48
49define zeroext i8 @and_ri_i8(i8 signext %a) {
50; CHECK-LABEL: and_ri_i8
51; CHECK:       and {{w[0-9]+}}, w0, #0xf
52  %1 = and i8 %a, 15
53  ret i8 %1
54}
55
56define zeroext i16 @and_ri_i16(i16 signext %a) {
57; CHECK-LABEL: and_ri_i16
58; CHECK:       and {{w[0-9]+}}, w0, #0xff
59  %1 = and i16 %a, 255
60  ret i16 %1
61}
62
63define i32 @and_ri_i32(i32 %a) {
64; CHECK-LABEL: and_ri_i32
65; CHECK:       and w0, w0, #0xff
66  %1 = and i32 %a, 255
67  ret i32 %1
68}
69
70define i64 @and_ri_i64(i64 %a) {
71; CHECK-LABEL: and_ri_i64
72; CHECK:       and x0, x0, #0xff
73  %1 = and i64 %a, 255
74  ret i64 %1
75}
76
77define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {
78; CHECK-LABEL: and_rs_i8
79; CHECK:       and [[REG:w[0-9]+]], w0, w1, lsl #4
80; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
81  %1 = shl i8 %b, 4
82  %2 = and i8 %a, %1
83  ret i8 %2
84}
85
86define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {
87; CHECK-LABEL: and_rs_i16
88; CHECK:       and [[REG:w[0-9]+]], w0, w1, lsl #8
89; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
90  %1 = shl i16 %b, 8
91  %2 = and i16 %a, %1
92  ret i16 %2
93}
94
95define i32 @and_rs_i32(i32 %a, i32 %b) {
96; CHECK-LABEL: and_rs_i32
97; CHECK:       and w0, w0, w1, lsl #8
98  %1 = shl i32 %b, 8
99  %2 = and i32 %a, %1
100  ret i32 %2
101}
102
103define i64 @and_rs_i64(i64 %a, i64 %b) {
104; CHECK-LABEL: and_rs_i64
105; CHECK:       and x0, x0, x1, lsl #8
106  %1 = shl i64 %b, 8
107  %2 = and i64 %a, %1
108  ret i64 %2
109}
110
111define i32 @and_mul_i32(i32 %a, i32 %b) {
112; CHECK-LABEL: and_mul_i32
113; CHECK:       and w0, w0, w1, lsl #2
114  %1 = mul i32 %b, 4
115  %2 = and i32 %a, %1
116  ret i32 %2
117}
118
119define i64 @and_mul_i64(i64 %a, i64 %b) {
120; CHECK-LABEL: and_mul_i64
121; CHECK:       and x0, x0, x1, lsl #2
122  %1 = mul i64 %b, 4
123  %2 = and i64 %a, %1
124  ret i64 %2
125}
126
127; OR
128define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {
129; CHECK-LABEL: or_rr_i1
130; CHECK:       orr [[REG:w[0-9]+]], w0, w1
131  %1 = or i1 %a, %b
132  ret i1 %1
133}
134
135define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {
136; CHECK-LABEL: or_rr_i8
137; CHECK:       orr [[REG:w[0-9]+]], w0, w1
138; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xff
139  %1 = or i8 %a, %b
140  ret i8 %1
141}
142
143define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {
144; CHECK-LABEL: or_rr_i16
145; CHECK:       orr [[REG:w[0-9]+]], w0, w1
146; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xffff
147  %1 = or i16 %a, %b
148  ret i16 %1
149}
150
151define i32 @or_rr_i32(i32 %a, i32 %b) {
152; CHECK-LABEL: or_rr_i32
153; CHECK:       orr w0, w0, w1
154  %1 = or i32 %a, %b
155  ret i32 %1
156}
157
158define i64 @or_rr_i64(i64 %a, i64 %b) {
159; CHECK-LABEL: or_rr_i64
160; CHECK:       orr x0, x0, x1
161  %1 = or i64 %a, %b
162  ret i64 %1
163}
164
165define zeroext i8 @or_ri_i8(i8 %a) {
166; CHECK-LABEL: or_ri_i8
167; CHECK:       orr [[REG:w[0-9]+]], w0, #0xf
168; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xff
169  %1 = or i8 %a, 15
170  ret i8 %1
171}
172
173define zeroext i16 @or_ri_i16(i16 %a) {
174; CHECK-LABEL: or_ri_i16
175; CHECK:       orr [[REG:w[0-9]+]], w0, #0xff
176; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xffff
177  %1 = or i16 %a, 255
178  ret i16 %1
179}
180
181define i32 @or_ri_i32(i32 %a) {
182; CHECK-LABEL: or_ri_i32
183; CHECK:       orr w0, w0, #0xff
184  %1 = or i32 %a, 255
185  ret i32 %1
186}
187
188define i64 @or_ri_i64(i64 %a) {
189; CHECK-LABEL: or_ri_i64
190; CHECK:       orr x0, x0, #0xff
191  %1 = or i64 %a, 255
192  ret i64 %1
193}
194
195define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {
196; CHECK-LABEL: or_rs_i8
197; CHECK:       orr [[REG:w[0-9]+]], w0, w1, lsl #4
198; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
199  %1 = shl i8 %b, 4
200  %2 = or i8 %a, %1
201  ret i8 %2
202}
203
204define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {
205; CHECK-LABEL: or_rs_i16
206; CHECK:       orr [[REG:w[0-9]+]], w0, w1, lsl #8
207; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
208  %1 = shl i16 %b, 8
209  %2 = or i16 %a, %1
210  ret i16 %2
211}
212
213define i32 @or_rs_i32(i32 %a, i32 %b) {
214; CHECK-LABEL: or_rs_i32
215; CHECK:       orr w0, w0, w1, lsl #8
216  %1 = shl i32 %b, 8
217  %2 = or i32 %a, %1
218  ret i32 %2
219}
220
221define i64 @or_rs_i64(i64 %a, i64 %b) {
222; CHECK-LABEL: or_rs_i64
223; CHECK:       orr x0, x0, x1, lsl #8
224  %1 = shl i64 %b, 8
225  %2 = or i64 %a, %1
226  ret i64 %2
227}
228
229define i32 @or_mul_i32(i32 %a, i32 %b) {
230; CHECK-LABEL: or_mul_i32
231; CHECK:       orr w0, w0, w1, lsl #2
232  %1 = mul i32 %b, 4
233  %2 = or i32 %a, %1
234  ret i32 %2
235}
236
237define i64 @or_mul_i64(i64 %a, i64 %b) {
238; CHECK-LABEL: or_mul_i64
239; CHECK:       orr x0, x0, x1, lsl #2
240  %1 = mul i64 %b, 4
241  %2 = or i64 %a, %1
242  ret i64 %2
243}
244
245; XOR
246define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {
247; CHECK-LABEL: xor_rr_i1
248; CHECK:       eor [[REG:w[0-9]+]], w0, w1
249  %1 = xor i1 %a, %b
250  ret i1 %1
251}
252
253define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {
254; CHECK-LABEL: xor_rr_i8
255; CHECK:       eor [[REG:w[0-9]+]], w0, w1
256; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xff
257  %1 = xor i8 %a, %b
258  ret i8 %1
259}
260
261define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {
262; CHECK-LABEL: xor_rr_i16
263; CHECK:       eor [[REG:w[0-9]+]], w0, w1
264; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xffff
265  %1 = xor i16 %a, %b
266  ret i16 %1
267}
268
269define i32 @xor_rr_i32(i32 %a, i32 %b) {
270; CHECK-LABEL: xor_rr_i32
271; CHECK:       eor w0, w0, w1
272  %1 = xor i32 %a, %b
273  ret i32 %1
274}
275
276define i64 @xor_rr_i64(i64 %a, i64 %b) {
277; CHECK-LABEL: xor_rr_i64
278; CHECK:       eor x0, x0, x1
279  %1 = xor i64 %a, %b
280  ret i64 %1
281}
282
283define zeroext i8 @xor_ri_i8(i8 signext %a) {
284; CHECK-LABEL: xor_ri_i8
285; CHECK:       eor [[REG:w[0-9]+]], w0, #0xf
286; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xff
287  %1 = xor i8 %a, 15
288  ret i8 %1
289}
290
291define zeroext i16 @xor_ri_i16(i16 signext %a) {
292; CHECK-LABEL: xor_ri_i16
293; CHECK:       eor [[REG:w[0-9]+]], w0, #0xff
294; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], #0xffff
295  %1 = xor i16 %a, 255
296  ret i16 %1
297}
298
299define i32 @xor_ri_i32(i32 %a) {
300; CHECK-LABEL: xor_ri_i32
301; CHECK:       eor w0, w0, #0xff
302  %1 = xor i32 %a, 255
303  ret i32 %1
304}
305
306define i64 @xor_ri_i64(i64 %a) {
307; CHECK-LABEL: xor_ri_i64
308; CHECK:       eor x0, x0, #0xff
309  %1 = xor i64 %a, 255
310  ret i64 %1
311}
312
313define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {
314; CHECK-LABEL: xor_rs_i8
315; CHECK:       eor [[REG:w[0-9]+]], w0, w1, lsl #4
316; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
317  %1 = shl i8 %b, 4
318  %2 = xor i8 %a, %1
319  ret i8 %2
320}
321
322define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {
323; CHECK-LABEL: xor_rs_i16
324; CHECK:       eor [[REG:w[0-9]+]], w0, w1, lsl #8
325; CHECK-NEXT:  and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
326  %1 = shl i16 %b, 8
327  %2 = xor i16 %a, %1
328  ret i16 %2
329}
330
331define i32 @xor_rs_i32(i32 %a, i32 %b) {
332; CHECK-LABEL: xor_rs_i32
333; CHECK:       eor w0, w0, w1, lsl #8
334  %1 = shl i32 %b, 8
335  %2 = xor i32 %a, %1
336  ret i32 %2
337}
338
339define i64 @xor_rs_i64(i64 %a, i64 %b) {
340; CHECK-LABEL: xor_rs_i64
341; CHECK:       eor x0, x0, x1, lsl #8
342  %1 = shl i64 %b, 8
343  %2 = xor i64 %a, %1
344  ret i64 %2
345}
346
347define i32 @xor_mul_i32(i32 %a, i32 %b) {
348; CHECK-LABEL: xor_mul_i32
349; CHECK:       eor w0, w0, w1, lsl #2
350  %1 = mul i32 %b, 4
351  %2 = xor i32 %a, %1
352  ret i32 %2
353}
354
355define i64 @xor_mul_i64(i64 %a, i64 %b) {
356; CHECK-LABEL: xor_mul_i64
357; CHECK:       eor x0, x0, x1, lsl #2
358  %1 = mul i64 %b, 4
359  %2 = xor i64 %a, %1
360  ret i64 %2
361}
362
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