source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/fp16-vector-nvcast.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 2.9 KB
Line 
1; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
2
3; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
4define void @nvcast_v2i32(<4 x half>* %a) #0 {
5; CHECK-LABEL: nvcast_v2i32:
6; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #0xab, lsl #16
7; CHECK-NEXT: str d[[REG]], [x0]
8; CHECK-NEXT: ret
9  store volatile <4 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <4 x half>* %a
10  ret void
11}
12
13
14; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
15define void @nvcast_v4i16(<4 x half>* %a) #0 {
16; CHECK-LABEL: nvcast_v4i16:
17; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #0xab
18; CHECK-NEXT: str d[[REG]], [x0]
19; CHECK-NEXT: ret
20  store volatile <4 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <4 x half>* %a
21  ret void
22}
23
24
25; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
26define void @nvcast_v8i8(<4 x half>* %a) #0 {
27; CHECK-LABEL: nvcast_v8i8:
28; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #0xab
29; CHECK-NEXT: str d[[REG]], [x0]
30; CHECK-NEXT: ret
31  store volatile <4 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <4 x half>* %a
32  ret void
33}
34
35
36; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
37define void @nvcast_f64(<4 x half>* %a) #0 {
38; CHECK-LABEL: nvcast_f64:
39; CHECK-NEXT: movi d[[REG:[0-9]+]], #0000000000000000
40; CHECK-NEXT: str d[[REG]], [x0]
41; CHECK-NEXT: ret
42  store volatile <4 x half> zeroinitializer, <4 x half>* %a
43  ret void
44}
45
46; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
47define void @nvcast_v4i32(<8 x half>* %a) #0 {
48; CHECK-LABEL: nvcast_v4i32:
49; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #0xab, lsl #16
50; CHECK-NEXT: str q[[REG]], [x0]
51; CHECK-NEXT: ret
52  store volatile <8 x half> <half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB, half 0xH0000, half 0xH00AB>, <8 x half>* %a
53  ret void
54}
55
56
57; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
58define void @nvcast_v8i16(<8 x half>* %a) #0 {
59; CHECK-LABEL: nvcast_v8i16:
60; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #0xab
61; CHECK-NEXT: str q[[REG]], [x0]
62; CHECK-NEXT: ret
63  store volatile <8 x half> <half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB, half 0xH00AB>, <8 x half>* %a
64  ret void
65}
66
67
68; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
69define void @nvcast_v16i8(<8 x half>* %a) #0 {
70; CHECK-LABEL: nvcast_v16i8:
71; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #0xab
72; CHECK-NEXT: str q[[REG]], [x0]
73; CHECK-NEXT: ret
74  store volatile <8 x half> <half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB, half 0xHABAB>, <8 x half>* %a
75  ret void
76}
77
78
79; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
80define void @nvcast_v2i64(<8 x half>* %a) #0 {
81; CHECK-LABEL: nvcast_v2i64:
82; CHECK-NEXT: movi v[[REG:[0-9]+]].2d, #0000000000000000
83; CHECK-NEXT: str q[[REG]], [x0]
84; CHECK-NEXT: ret
85  store volatile <8 x half> zeroinitializer, <8 x half>* %a
86  ret void
87}
88
89attributes #0 = { nounwind }
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