source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/i1-contents.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.5 KB
Line 
1; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
2%big = type i32
3
4@var = global %big 0
5
6; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
7; 32-bits.
8define void @consume_i1_arg(i1 %in) {
9; CHECK-LABEL: consume_i1_arg:
10; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
11; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
12  %val = zext i1 %in to %big
13  store %big %val, %big* @var
14  ret void
15}
16
17; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
18; 32-bits (doesn't really matter if it's from 1 or 8 bits).
19define void @consume_i1_ret() {
20; CHECK-LABEL: consume_i1_ret:
21; CHECK: bl produce_i1_ret
22; CHECK: and [[BOOL32:w[0-9]+]], w0, #{{0x1|0xff}}
23; CHECK: str [[BOOL32]], [{{x[0-9]+}}, :lo12:var]
24  %val1 = call i1 @produce_i1_ret()
25  %val = zext i1 %val1 to %big
26  store %big %val, %big* @var
27  ret void
28}
29
30; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
31define i1 @produce_i1_ret() {
32; CHECK-LABEL: produce_i1_ret:
33; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
34; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
35  %val = load %big, %big* @var
36  %val1 = trunc %big %val to i1
37  ret i1 %val1
38}
39
40define void @produce_i1_arg() {
41; CHECK-LABEL: produce_i1_arg:
42; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var]
43; CHECK: and w0, [[VAR32]], #{{0x1|0xff}}
44; CHECK: bl consume_i1_arg
45  %val = load %big, %big* @var
46  %val1 = trunc %big %val to i1
47  call void @consume_i1_arg(i1 %val1)
48  ret void
49}
50
51
52;define zeroext i1 @foo(i8 %in) {
53;  %val = trunc i8 %in to i1
54;  ret i1 %val
55;}
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