source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/movw-consts.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 2.4 KB
Line 
1; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK
2
3define i64 @test0() {
4; CHECK-LABEL: test0:
5; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
6; CHECK: mov x0, xzr
7  ret i64 0
8}
9
10define i64 @test1() {
11; CHECK-LABEL: test1:
12; CHECK: orr w0, wzr, #0x1
13  ret i64 1
14}
15
16define i64 @test2() {
17; CHECK-LABEL: test2:
18; CHECK: orr w0, wzr, #0xffff
19  ret i64 65535
20}
21
22define i64 @test3() {
23; CHECK-LABEL: test3:
24; CHECK: orr w0, wzr, #0x10000
25  ret i64 65536
26}
27
28define i64 @test4() {
29; CHECK-LABEL: test4:
30; CHECK: orr w0, wzr, #0xffff0000
31  ret i64 4294901760
32}
33
34define i64 @test5() {
35; CHECK-LABEL: test5:
36; CHECK: orr x0, xzr, #0x100000000
37  ret i64 4294967296
38}
39
40define i64 @test6() {
41; CHECK-LABEL: test6:
42; CHECK: orr x0, xzr, #0xffff00000000
43  ret i64 281470681743360
44}
45
46define i64 @test7() {
47; CHECK-LABEL: test7:
48; CHECK: orr x0, xzr, #0x1000000000000
49  ret i64 281474976710656
50}
51
52; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
53; couldn't. Useful even for i64
54define i64 @test8() {
55; CHECK-LABEL: test8:
56; CHECK: movn w0, #{{60875|0xedcb}}
57  ret i64 4294906420
58}
59
60define i64 @test9() {
61; CHECK-LABEL: test9:
62; CHECK: movn x0, #0
63  ret i64 -1
64}
65
66define i64 @test10() {
67; CHECK-LABEL: test10:
68; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16
69  ret i64 18446744069720047615
70}
71
72; For reasonably legitimate reasons returning an i32 results in the
73; selection of an i64 constant, so we need a different idiom to test that selection
74@var32 = global i32 0
75
76define void @test11() {
77; CHECK-LABEL: test11:
78; CHECK: str wzr
79  store i32 0, i32* @var32
80  ret void
81}
82
83define void @test12() {
84; CHECK-LABEL: test12:
85; CHECK: orr {{w[0-9]+}}, wzr, #0x1
86  store i32 1, i32* @var32
87  ret void
88}
89
90define void @test13() {
91; CHECK-LABEL: test13:
92; CHECK: orr {{w[0-9]+}}, wzr, #0xffff
93  store i32 65535, i32* @var32
94  ret void
95}
96
97define void @test14() {
98; CHECK-LABEL: test14:
99; CHECK: orr {{w[0-9]+}}, wzr, #0x10000
100  store i32 65536, i32* @var32
101  ret void
102}
103
104define void @test15() {
105; CHECK-LABEL: test15:
106; CHECK: orr {{w[0-9]+}}, wzr, #0xffff0000
107  store i32 4294901760, i32* @var32
108  ret void
109}
110
111define void @test16() {
112; CHECK-LABEL: test16:
113; CHECK: movn {{w[0-9]+}}, #0
114  store i32 -1, i32* @var32
115  ret void
116}
117
118define i64 @test17() {
119; CHECK-LABEL: test17:
120
121  ; Mustn't MOVN w0 here.
122; CHECK: orr x0, xzr, #0xfffffffffffffffd
123  ret i64 -3
124}
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