source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/neon-compare-instructions.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2
3define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
4; CHECK-LABEL: cmeq8xi8:
5; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6        %tmp3 = icmp eq <8 x i8> %A, %B;
7   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
8        ret <8 x i8> %tmp4
9}
10
11define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
12; CHECK-LABEL: cmeq16xi8:
13; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
14        %tmp3 = icmp eq <16 x i8> %A, %B;
15   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
16        ret <16 x i8> %tmp4
17}
18
19define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
20; CHECK-LABEL: cmeq4xi16:
21; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
22        %tmp3 = icmp eq <4 x i16> %A, %B;
23   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
24        ret <4 x i16> %tmp4
25}
26
27define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
28; CHECK-LABEL: cmeq8xi16:
29; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
30        %tmp3 = icmp eq <8 x i16> %A, %B;
31   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
32        ret <8 x i16> %tmp4
33}
34
35define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
36; CHECK-LABEL: cmeq2xi32:
37; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
38        %tmp3 = icmp eq <2 x i32> %A, %B;
39   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
40        ret <2 x i32> %tmp4
41}
42
43define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
44; CHECK-LABEL: cmeq4xi32:
45; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
46        %tmp3 = icmp eq <4 x i32> %A, %B;
47   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
48        ret <4 x i32> %tmp4
49}
50
51define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
52; CHECK-LABEL: cmeq2xi64:
53; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
54        %tmp3 = icmp eq <2 x i64> %A, %B;
55   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
56        ret <2 x i64> %tmp4
57}
58
59define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
60; CHECK-LABEL: cmne8xi8:
61; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
62; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
63        %tmp3 = icmp ne <8 x i8> %A, %B;
64   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
65        ret <8 x i8> %tmp4
66}
67
68define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
69; CHECK-LABEL: cmne16xi8:
70; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
71; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
72        %tmp3 = icmp ne <16 x i8> %A, %B;
73   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
74        ret <16 x i8> %tmp4
75}
76
77define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
78; CHECK-LABEL: cmne4xi16:
79; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
80; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
81        %tmp3 = icmp ne <4 x i16> %A, %B;
82   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
83        ret <4 x i16> %tmp4
84}
85
86define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
87; CHECK-LABEL: cmne8xi16:
88; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
89; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
90        %tmp3 = icmp ne <8 x i16> %A, %B;
91   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
92        ret <8 x i16> %tmp4
93}
94
95define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
96; CHECK-LABEL: cmne2xi32:
97; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
98; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
99        %tmp3 = icmp ne <2 x i32> %A, %B;
100   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
101        ret <2 x i32> %tmp4
102}
103
104define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
105; CHECK-LABEL: cmne4xi32:
106; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
107; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
108        %tmp3 = icmp ne <4 x i32> %A, %B;
109   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
110        ret <4 x i32> %tmp4
111}
112
113define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
114; CHECK-LABEL: cmne2xi64:
115; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
116; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
117        %tmp3 = icmp ne <2 x i64> %A, %B;
118   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
119        ret <2 x i64> %tmp4
120}
121
122define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
123; CHECK-LABEL: cmgt8xi8:
124; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
125        %tmp3 = icmp sgt <8 x i8> %A, %B;
126   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
127        ret <8 x i8> %tmp4
128}
129
130define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
131; CHECK-LABEL: cmgt16xi8:
132; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
133        %tmp3 = icmp sgt <16 x i8> %A, %B;
134   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
135        ret <16 x i8> %tmp4
136}
137
138define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
139; CHECK-LABEL: cmgt4xi16:
140; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
141        %tmp3 = icmp sgt <4 x i16> %A, %B;
142   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
143        ret <4 x i16> %tmp4
144}
145
146define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
147; CHECK-LABEL: cmgt8xi16:
148; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
149        %tmp3 = icmp sgt <8 x i16> %A, %B;
150   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
151        ret <8 x i16> %tmp4
152}
153
154define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
155; CHECK-LABEL: cmgt2xi32:
156; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
157        %tmp3 = icmp sgt <2 x i32> %A, %B;
158   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
159        ret <2 x i32> %tmp4
160}
161
162define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
163; CHECK-LABEL: cmgt4xi32:
164; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
165        %tmp3 = icmp sgt <4 x i32> %A, %B;
166   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
167        ret <4 x i32> %tmp4
168}
169
170define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
171; CHECK-LABEL: cmgt2xi64:
172; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
173        %tmp3 = icmp sgt <2 x i64> %A, %B;
174   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
175        ret <2 x i64> %tmp4
176}
177
178define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
179; CHECK-LABEL: cmlt8xi8:
180; Using registers other than v0, v1 are possible, but would be odd.
181; LT implemented as GT, so check reversed operands.
182; CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b
183        %tmp3 = icmp slt <8 x i8> %A, %B;
184   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
185        ret <8 x i8> %tmp4
186}
187
188define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
189; CHECK-LABEL: cmlt16xi8:
190; Using registers other than v0, v1 are possible, but would be odd.
191; LT implemented as GT, so check reversed operands.
192; CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b
193        %tmp3 = icmp slt <16 x i8> %A, %B;
194   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
195        ret <16 x i8> %tmp4
196}
197
198define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
199; CHECK-LABEL: cmlt4xi16:
200; Using registers other than v0, v1 are possible, but would be odd.
201; LT implemented as GT, so check reversed operands.
202; CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h
203        %tmp3 = icmp slt <4 x i16> %A, %B;
204   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
205        ret <4 x i16> %tmp4
206}
207
208define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
209; CHECK-LABEL: cmlt8xi16:
210; Using registers other than v0, v1 are possible, but would be odd.
211; LT implemented as GT, so check reversed operands.
212; CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h
213        %tmp3 = icmp slt <8 x i16> %A, %B;
214   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
215        ret <8 x i16> %tmp4
216}
217
218define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
219; CHECK-LABEL: cmlt2xi32:
220; Using registers other than v0, v1 are possible, but would be odd.
221; LT implemented as GT, so check reversed operands.
222; CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
223        %tmp3 = icmp slt <2 x i32> %A, %B;
224   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
225        ret <2 x i32> %tmp4
226}
227
228define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
229; CHECK-LABEL: cmlt4xi32:
230; Using registers other than v0, v1 are possible, but would be odd.
231; LT implemented as GT, so check reversed operands.
232; CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
233        %tmp3 = icmp slt <4 x i32> %A, %B;
234   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
235        ret <4 x i32> %tmp4
236}
237
238define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
239; CHECK-LABEL: cmlt2xi64:
240; Using registers other than v0, v1 are possible, but would be odd.
241; LT implemented as GT, so check reversed operands.
242; CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
243        %tmp3 = icmp slt <2 x i64> %A, %B;
244   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
245        ret <2 x i64> %tmp4
246}
247
248define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
249; CHECK-LABEL: cmge8xi8:
250; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
251        %tmp3 = icmp sge <8 x i8> %A, %B;
252   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
253        ret <8 x i8> %tmp4
254}
255
256define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
257; CHECK-LABEL: cmge16xi8:
258; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
259        %tmp3 = icmp sge <16 x i8> %A, %B;
260   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
261        ret <16 x i8> %tmp4
262}
263
264define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
265; CHECK-LABEL: cmge4xi16:
266; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
267        %tmp3 = icmp sge <4 x i16> %A, %B;
268   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
269        ret <4 x i16> %tmp4
270}
271
272define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
273; CHECK-LABEL: cmge8xi16:
274; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
275        %tmp3 = icmp sge <8 x i16> %A, %B;
276   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
277        ret <8 x i16> %tmp4
278}
279
280define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
281; CHECK-LABEL: cmge2xi32:
282; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
283        %tmp3 = icmp sge <2 x i32> %A, %B;
284   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
285        ret <2 x i32> %tmp4
286}
287
288define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
289; CHECK-LABEL: cmge4xi32:
290; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
291        %tmp3 = icmp sge <4 x i32> %A, %B;
292   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
293        ret <4 x i32> %tmp4
294}
295
296define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
297; CHECK-LABEL: cmge2xi64:
298; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
299        %tmp3 = icmp sge <2 x i64> %A, %B;
300   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
301        ret <2 x i64> %tmp4
302}
303
304define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
305; CHECK-LABEL: cmle8xi8:
306; Using registers other than v0, v1 are possible, but would be odd.
307; LE implemented as GE, so check reversed operands.
308; CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b
309        %tmp3 = icmp sle <8 x i8> %A, %B;
310   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
311        ret <8 x i8> %tmp4
312}
313
314define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
315; CHECK-LABEL: cmle16xi8:
316; Using registers other than v0, v1 are possible, but would be odd.
317; LE implemented as GE, so check reversed operands.
318; CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b
319        %tmp3 = icmp sle <16 x i8> %A, %B;
320   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
321        ret <16 x i8> %tmp4
322}
323
324define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
325; CHECK-LABEL: cmle4xi16:
326; Using registers other than v0, v1 are possible, but would be odd.
327; LE implemented as GE, so check reversed operands.
328; CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h
329        %tmp3 = icmp sle <4 x i16> %A, %B;
330   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
331        ret <4 x i16> %tmp4
332}
333
334define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
335; CHECK-LABEL: cmle8xi16:
336; Using registers other than v0, v1 are possible, but would be odd.
337; LE implemented as GE, so check reversed operands.
338; CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h
339        %tmp3 = icmp sle <8 x i16> %A, %B;
340   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
341        ret <8 x i16> %tmp4
342}
343
344define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
345; CHECK-LABEL: cmle2xi32:
346; Using registers other than v0, v1 are possible, but would be odd.
347; LE implemented as GE, so check reversed operands.
348; CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s
349        %tmp3 = icmp sle <2 x i32> %A, %B;
350   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
351        ret <2 x i32> %tmp4
352}
353
354define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
355; CHECK-LABEL: cmle4xi32:
356; Using registers other than v0, v1 are possible, but would be odd.
357; LE implemented as GE, so check reversed operands.
358; CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s
359        %tmp3 = icmp sle <4 x i32> %A, %B;
360   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
361        ret <4 x i32> %tmp4
362}
363
364define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
365; CHECK-LABEL: cmle2xi64:
366; Using registers other than v0, v1 are possible, but would be odd.
367; LE implemented as GE, so check reversed operands.
368; CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d
369        %tmp3 = icmp sle <2 x i64> %A, %B;
370   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
371        ret <2 x i64> %tmp4
372}
373
374define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
375; CHECK-LABEL: cmhi8xi8:
376; CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
377        %tmp3 = icmp ugt <8 x i8> %A, %B;
378   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
379        ret <8 x i8> %tmp4
380}
381
382define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
383; CHECK-LABEL: cmhi16xi8:
384; CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
385        %tmp3 = icmp ugt <16 x i8> %A, %B;
386   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
387        ret <16 x i8> %tmp4
388}
389
390define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
391; CHECK-LABEL: cmhi4xi16:
392; CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
393        %tmp3 = icmp ugt <4 x i16> %A, %B;
394   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
395        ret <4 x i16> %tmp4
396}
397
398define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
399; CHECK-LABEL: cmhi8xi16:
400; CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
401        %tmp3 = icmp ugt <8 x i16> %A, %B;
402   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
403        ret <8 x i16> %tmp4
404}
405
406define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
407; CHECK-LABEL: cmhi2xi32:
408; CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
409        %tmp3 = icmp ugt <2 x i32> %A, %B;
410   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
411        ret <2 x i32> %tmp4
412}
413
414define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
415; CHECK-LABEL: cmhi4xi32:
416; CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
417        %tmp3 = icmp ugt <4 x i32> %A, %B;
418   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
419        ret <4 x i32> %tmp4
420}
421
422define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
423; CHECK-LABEL: cmhi2xi64:
424; CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
425        %tmp3 = icmp ugt <2 x i64> %A, %B;
426   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
427        ret <2 x i64> %tmp4
428}
429
430define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
431; CHECK-LABEL: cmlo8xi8:
432; Using registers other than v0, v1 are possible, but would be odd.
433; LO implemented as HI, so check reversed operands.
434; CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b
435        %tmp3 = icmp ult <8 x i8> %A, %B;
436   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
437        ret <8 x i8> %tmp4
438}
439
440define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
441; CHECK-LABEL: cmlo16xi8:
442; Using registers other than v0, v1 are possible, but would be odd.
443; LO implemented as HI, so check reversed operands.
444; CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
445        %tmp3 = icmp ult <16 x i8> %A, %B;
446   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
447        ret <16 x i8> %tmp4
448}
449
450define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
451; CHECK-LABEL: cmlo4xi16:
452; Using registers other than v0, v1 are possible, but would be odd.
453; LO implemented as HI, so check reversed operands.
454; CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
455        %tmp3 = icmp ult <4 x i16> %A, %B;
456   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
457        ret <4 x i16> %tmp4
458}
459
460define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
461; CHECK-LABEL: cmlo8xi16:
462; Using registers other than v0, v1 are possible, but would be odd.
463; LO implemented as HI, so check reversed operands.
464; CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
465        %tmp3 = icmp ult <8 x i16> %A, %B;
466   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
467        ret <8 x i16> %tmp4
468}
469
470define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
471; CHECK-LABEL: cmlo2xi32:
472; Using registers other than v0, v1 are possible, but would be odd.
473; LO implemented as HI, so check reversed operands.
474; CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
475        %tmp3 = icmp ult <2 x i32> %A, %B;
476   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
477        ret <2 x i32> %tmp4
478}
479
480define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
481; CHECK-LABEL: cmlo4xi32:
482; Using registers other than v0, v1 are possible, but would be odd.
483; LO implemented as HI, so check reversed operands.
484; CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
485        %tmp3 = icmp ult <4 x i32> %A, %B;
486   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
487        ret <4 x i32> %tmp4
488}
489
490define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
491; CHECK-LABEL: cmlo2xi64:
492; Using registers other than v0, v1 are possible, but would be odd.
493; LO implemented as HI, so check reversed operands.
494; CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
495        %tmp3 = icmp ult <2 x i64> %A, %B;
496   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
497        ret <2 x i64> %tmp4
498}
499
500define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
501; CHECK-LABEL: cmhs8xi8:
502; CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
503        %tmp3 = icmp uge <8 x i8> %A, %B;
504   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
505        ret <8 x i8> %tmp4
506}
507
508define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
509; CHECK-LABEL: cmhs16xi8:
510; CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
511        %tmp3 = icmp uge <16 x i8> %A, %B;
512   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
513        ret <16 x i8> %tmp4
514}
515
516define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
517; CHECK-LABEL: cmhs4xi16:
518; CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
519        %tmp3 = icmp uge <4 x i16> %A, %B;
520   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
521        ret <4 x i16> %tmp4
522}
523
524define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
525; CHECK-LABEL: cmhs8xi16:
526; CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
527        %tmp3 = icmp uge <8 x i16> %A, %B;
528   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
529        ret <8 x i16> %tmp4
530}
531
532define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
533; CHECK-LABEL: cmhs2xi32:
534; CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
535        %tmp3 = icmp uge <2 x i32> %A, %B;
536   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
537        ret <2 x i32> %tmp4
538}
539
540define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
541; CHECK-LABEL: cmhs4xi32:
542; CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
543        %tmp3 = icmp uge <4 x i32> %A, %B;
544   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
545        ret <4 x i32> %tmp4
546}
547
548define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
549; CHECK-LABEL: cmhs2xi64:
550; CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
551        %tmp3 = icmp uge <2 x i64> %A, %B;
552   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
553        ret <2 x i64> %tmp4
554}
555
556define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
557; CHECK-LABEL: cmls8xi8:
558; Using registers other than v0, v1 are possible, but would be odd.
559; LS implemented as HS, so check reversed operands.
560; CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
561        %tmp3 = icmp ule <8 x i8> %A, %B;
562   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
563        ret <8 x i8> %tmp4
564}
565
566define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
567; CHECK-LABEL: cmls16xi8:
568; Using registers other than v0, v1 are possible, but would be odd.
569; LS implemented as HS, so check reversed operands.
570; CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
571        %tmp3 = icmp ule <16 x i8> %A, %B;
572   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
573        ret <16 x i8> %tmp4
574}
575
576define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
577; CHECK-LABEL: cmls4xi16:
578; Using registers other than v0, v1 are possible, but would be odd.
579; LS implemented as HS, so check reversed operands.
580; CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
581        %tmp3 = icmp ule <4 x i16> %A, %B;
582   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
583        ret <4 x i16> %tmp4
584}
585
586define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
587; CHECK-LABEL: cmls8xi16:
588; Using registers other than v0, v1 are possible, but would be odd.
589; LS implemented as HS, so check reversed operands.
590; CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
591        %tmp3 = icmp ule <8 x i16> %A, %B;
592   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
593        ret <8 x i16> %tmp4
594}
595
596define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
597; CHECK-LABEL: cmls2xi32:
598; Using registers other than v0, v1 are possible, but would be odd.
599; LS implemented as HS, so check reversed operands.
600; CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
601        %tmp3 = icmp ule <2 x i32> %A, %B;
602   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
603        ret <2 x i32> %tmp4
604}
605
606define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
607; CHECK-LABEL: cmls4xi32:
608; Using registers other than v0, v1 are possible, but would be odd.
609; LS implemented as HS, so check reversed operands.
610; CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
611        %tmp3 = icmp ule <4 x i32> %A, %B;
612   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
613        ret <4 x i32> %tmp4
614}
615
616define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
617; CHECK-LABEL: cmls2xi64:
618; Using registers other than v0, v1 are possible, but would be odd.
619; LS implemented as HS, so check reversed operands.
620; CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
621        %tmp3 = icmp ule <2 x i64> %A, %B;
622   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
623        ret <2 x i64> %tmp4
624}
625
626define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
627; CHECK-LABEL: cmtst8xi8:
628; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
629        %tmp3 = and <8 x i8> %A, %B
630        %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
631   %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
632        ret <8 x i8> %tmp5
633}
634
635define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
636; CHECK-LABEL: cmtst16xi8:
637; CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
638        %tmp3 = and <16 x i8> %A, %B
639        %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
640   %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
641        ret <16 x i8> %tmp5
642}
643
644define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
645; CHECK-LABEL: cmtst4xi16:
646; CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
647        %tmp3 = and <4 x i16> %A, %B
648        %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
649   %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
650        ret <4 x i16> %tmp5
651}
652
653define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
654; CHECK-LABEL: cmtst8xi16:
655; CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
656        %tmp3 = and <8 x i16> %A, %B
657        %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
658   %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
659        ret <8 x i16> %tmp5
660}
661
662define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
663; CHECK-LABEL: cmtst2xi32:
664; CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
665        %tmp3 = and <2 x i32> %A, %B
666        %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
667   %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
668        ret <2 x i32> %tmp5
669}
670
671define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
672; CHECK-LABEL: cmtst4xi32:
673; CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
674        %tmp3 = and <4 x i32> %A, %B
675        %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
676   %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
677        ret <4 x i32> %tmp5
678}
679
680define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
681; CHECK-LABEL: cmtst2xi64:
682; CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
683        %tmp3 = and <2 x i64> %A, %B
684        %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
685   %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
686        ret <2 x i64> %tmp5
687}
688
689
690
691define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
692; CHECK-LABEL: cmeqz8xi8:
693; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
694        %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
695   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
696        ret <8 x i8> %tmp4
697}
698
699define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
700; CHECK-LABEL: cmeqz16xi8:
701; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
702        %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
703   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
704        ret <16 x i8> %tmp4
705}
706
707define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
708; CHECK-LABEL: cmeqz4xi16:
709; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
710        %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
711   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
712        ret <4 x i16> %tmp4
713}
714
715define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
716; CHECK-LABEL: cmeqz8xi16:
717; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
718        %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
719   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
720        ret <8 x i16> %tmp4
721}
722
723define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
724; CHECK-LABEL: cmeqz2xi32:
725; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
726        %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
727   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
728        ret <2 x i32> %tmp4
729}
730
731define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
732; CHECK-LABEL: cmeqz4xi32:
733; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
734        %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
735   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
736        ret <4 x i32> %tmp4
737}
738
739define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
740; CHECK-LABEL: cmeqz2xi64:
741; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
742        %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
743   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
744        ret <2 x i64> %tmp4
745}
746
747
748define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
749; CHECK-LABEL: cmgez8xi8:
750; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
751        %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
752   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
753        ret <8 x i8> %tmp4
754}
755
756define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
757; CHECK-LABEL: cmgez16xi8:
758; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
759        %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
760   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
761        ret <16 x i8> %tmp4
762}
763
764define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
765; CHECK-LABEL: cmgez4xi16:
766; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
767        %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
768   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
769        ret <4 x i16> %tmp4
770}
771
772define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
773; CHECK-LABEL: cmgez8xi16:
774; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
775        %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
776   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
777        ret <8 x i16> %tmp4
778}
779
780define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
781; CHECK-LABEL: cmgez2xi32:
782; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
783        %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
784   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
785        ret <2 x i32> %tmp4
786}
787
788define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
789; CHECK-LABEL: cmgez4xi32:
790; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
791        %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
792   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
793        ret <4 x i32> %tmp4
794}
795
796define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
797; CHECK-LABEL: cmgez2xi64:
798; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
799        %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
800   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
801        ret <2 x i64> %tmp4
802}
803
804
805define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
806; CHECK-LABEL: cmgtz8xi8:
807; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
808        %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
809   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
810        ret <8 x i8> %tmp4
811}
812
813define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
814; CHECK-LABEL: cmgtz16xi8:
815; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
816        %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
817   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
818        ret <16 x i8> %tmp4
819}
820
821define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
822; CHECK-LABEL: cmgtz4xi16:
823; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
824        %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
825   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
826        ret <4 x i16> %tmp4
827}
828
829define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
830; CHECK-LABEL: cmgtz8xi16:
831; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
832        %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
833   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
834        ret <8 x i16> %tmp4
835}
836
837define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
838; CHECK-LABEL: cmgtz2xi32:
839; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
840        %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
841   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
842        ret <2 x i32> %tmp4
843}
844
845define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
846; CHECK-LABEL: cmgtz4xi32:
847; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
848        %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
849   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
850        ret <4 x i32> %tmp4
851}
852
853define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
854; CHECK-LABEL: cmgtz2xi64:
855; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
856        %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
857   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
858        ret <2 x i64> %tmp4
859}
860
861define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
862; CHECK-LABEL: cmlez8xi8:
863; CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
864        %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
865   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
866        ret <8 x i8> %tmp4
867}
868
869define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
870; CHECK-LABEL: cmlez16xi8:
871; CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
872        %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
873   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
874        ret <16 x i8> %tmp4
875}
876
877define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
878; CHECK-LABEL: cmlez4xi16:
879; CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
880        %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
881   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
882        ret <4 x i16> %tmp4
883}
884
885define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
886; CHECK-LABEL: cmlez8xi16:
887; CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
888        %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
889   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
890        ret <8 x i16> %tmp4
891}
892
893define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
894; CHECK-LABEL: cmlez2xi32:
895; CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
896        %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
897   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
898        ret <2 x i32> %tmp4
899}
900
901define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
902; CHECK-LABEL: cmlez4xi32:
903; CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
904        %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
905   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
906        ret <4 x i32> %tmp4
907}
908
909define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
910; CHECK-LABEL: cmlez2xi64:
911; CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
912        %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
913   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
914        ret <2 x i64> %tmp4
915}
916
917define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
918; CHECK-LABEL: cmltz8xi8:
919; CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
920        %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
921   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
922        ret <8 x i8> %tmp4
923}
924
925define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
926; CHECK-LABEL: cmltz16xi8:
927; CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
928        %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
929   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
930        ret <16 x i8> %tmp4
931}
932
933define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
934; CHECK-LABEL: cmltz4xi16:
935; CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
936        %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
937   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
938        ret <4 x i16> %tmp4
939}
940
941define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
942; CHECK-LABEL: cmltz8xi16:
943; CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
944        %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
945   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
946        ret <8 x i16> %tmp4
947}
948
949define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
950; CHECK-LABEL: cmltz2xi32:
951; CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
952        %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
953   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
954        ret <2 x i32> %tmp4
955}
956
957define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
958; CHECK-LABEL: cmltz4xi32:
959; CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
960        %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
961   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
962        ret <4 x i32> %tmp4
963}
964
965define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
966; CHECK-LABEL: cmltz2xi64:
967; CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
968        %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
969   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
970        ret <2 x i64> %tmp4
971}
972
973define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
974; CHECK-LABEL: cmneqz8xi8:
975; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
976; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
977        %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
978   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
979        ret <8 x i8> %tmp4
980}
981
982define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
983; CHECK-LABEL: cmneqz16xi8:
984; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
985; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
986        %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
987   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
988        ret <16 x i8> %tmp4
989}
990
991define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
992; CHECK-LABEL: cmneqz4xi16:
993; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
994; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
995        %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
996   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
997        ret <4 x i16> %tmp4
998}
999
1000define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
1001; CHECK-LABEL: cmneqz8xi16:
1002; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
1003; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1004        %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
1005   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1006        ret <8 x i16> %tmp4
1007}
1008
1009define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
1010; CHECK-LABEL: cmneqz2xi32:
1011; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
1012; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1013        %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
1014   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1015        ret <2 x i32> %tmp4
1016}
1017
1018define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
1019; CHECK-LABEL: cmneqz4xi32:
1020; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
1021; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1022        %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
1023   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1024        ret <4 x i32> %tmp4
1025}
1026
1027define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
1028; CHECK-LABEL: cmneqz2xi64:
1029; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
1030; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1031        %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
1032   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1033        ret <2 x i64> %tmp4
1034}
1035
1036define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
1037; CHECK-LABEL: cmhsz8xi8:
1038; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1039; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1040        %tmp3 = icmp uge <8 x i8> %A, zeroinitializer;
1041   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1042        ret <8 x i8> %tmp4
1043}
1044
1045define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
1046; CHECK-LABEL: cmhsz16xi8:
1047; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1048; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1049        %tmp3 = icmp uge <16 x i8> %A, zeroinitializer;
1050   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1051        ret <16 x i8> %tmp4
1052}
1053
1054define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
1055; CHECK-LABEL: cmhsz4xi16:
1056; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1057; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1058        %tmp3 = icmp uge <4 x i16> %A, zeroinitializer;
1059   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1060        ret <4 x i16> %tmp4
1061}
1062
1063define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
1064; CHECK-LABEL: cmhsz8xi16:
1065; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1066; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1067        %tmp3 = icmp uge <8 x i16> %A, zeroinitializer;
1068   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1069        ret <8 x i16> %tmp4
1070}
1071
1072define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
1073; CHECK-LABEL: cmhsz2xi32:
1074; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1075; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1076        %tmp3 = icmp uge <2 x i32> %A, zeroinitializer;
1077   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1078        ret <2 x i32> %tmp4
1079}
1080
1081define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
1082; CHECK-LABEL: cmhsz4xi32:
1083; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1084; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1085        %tmp3 = icmp uge <4 x i32> %A, zeroinitializer;
1086   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1087        ret <4 x i32> %tmp4
1088}
1089
1090define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
1091; CHECK-LABEL: cmhsz2xi64:
1092; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1093; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1094        %tmp3 = icmp uge <2 x i64> %A, zeroinitializer;
1095   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1096        ret <2 x i64> %tmp4
1097}
1098
1099
1100define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
1101; CHECK-LABEL: cmhiz8xi8:
1102; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1103; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1104        %tmp3 = icmp ugt <8 x i8> %A, zeroinitializer;
1105   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1106        ret <8 x i8> %tmp4
1107}
1108
1109define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
1110; CHECK-LABEL: cmhiz16xi8:
1111; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1112; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1113        %tmp3 = icmp ugt <16 x i8> %A, zeroinitializer;
1114   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1115        ret <16 x i8> %tmp4
1116}
1117
1118define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
1119; CHECK-LABEL: cmhiz4xi16:
1120; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1121; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1122        %tmp3 = icmp ugt <4 x i16> %A, zeroinitializer;
1123   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1124        ret <4 x i16> %tmp4
1125}
1126
1127define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
1128; CHECK-LABEL: cmhiz8xi16:
1129; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1130; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1131        %tmp3 = icmp ugt <8 x i16> %A, zeroinitializer;
1132   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1133        ret <8 x i16> %tmp4
1134}
1135
1136define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
1137; CHECK-LABEL: cmhiz2xi32:
1138; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1139; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1140        %tmp3 = icmp ugt <2 x i32> %A, zeroinitializer;
1141   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1142        ret <2 x i32> %tmp4
1143}
1144
1145define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
1146; CHECK-LABEL: cmhiz4xi32:
1147; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1148; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1149        %tmp3 = icmp ugt <4 x i32> %A, zeroinitializer;
1150   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1151        ret <4 x i32> %tmp4
1152}
1153
1154define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
1155; CHECK-LABEL: cmhiz2xi64:
1156; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1157; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1158        %tmp3 = icmp ugt <2 x i64> %A, zeroinitializer;
1159   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1160        ret <2 x i64> %tmp4
1161}
1162
1163define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
1164; CHECK-LABEL: cmlsz8xi8:
1165; Using registers other than v0, v1 are possible, but would be odd.
1166; LS implemented as HS, so check reversed operands.
1167; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1168; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
1169        %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
1170   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1171        ret <8 x i8> %tmp4
1172}
1173
1174define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
1175; CHECK-LABEL: cmlsz16xi8:
1176; Using registers other than v0, v1 are possible, but would be odd.
1177; LS implemented as HS, so check reversed operands.
1178; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1179; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
1180        %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
1181   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1182        ret <16 x i8> %tmp4
1183}
1184
1185define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
1186; CHECK-LABEL: cmlsz4xi16:
1187; Using registers other than v0, v1 are possible, but would be odd.
1188; LS implemented as HS, so check reversed operands.
1189; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1190; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
1191        %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
1192   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1193        ret <4 x i16> %tmp4
1194}
1195
1196define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
1197; CHECK-LABEL: cmlsz8xi16:
1198; Using registers other than v0, v1 are possible, but would be odd.
1199; LS implemented as HS, so check reversed operands.
1200; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1201; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
1202        %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
1203   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1204        ret <8 x i16> %tmp4
1205}
1206
1207define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
1208; CHECK-LABEL: cmlsz2xi32:
1209; Using registers other than v0, v1 are possible, but would be odd.
1210; LS implemented as HS, so check reversed operands.
1211; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1212; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
1213        %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
1214   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1215        ret <2 x i32> %tmp4
1216}
1217
1218define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
1219; CHECK-LABEL: cmlsz4xi32:
1220; Using registers other than v0, v1 are possible, but would be odd.
1221; LS implemented as HS, so check reversed operands.
1222; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1223; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
1224        %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
1225   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1226        ret <4 x i32> %tmp4
1227}
1228
1229define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
1230; CHECK-LABEL: cmlsz2xi64:
1231; Using registers other than v0, v1 are possible, but would be odd.
1232; LS implemented as HS, so check reversed operands.
1233; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1234; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
1235        %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
1236   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1237        ret <2 x i64> %tmp4
1238}
1239
1240define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
1241; CHECK-LABEL: cmloz8xi8:
1242; Using registers other than v0, v1 are possible, but would be odd.
1243; LO implemented as HI, so check reversed operands.
1244; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1245; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b
1246        %tmp3 = icmp ult <8 x i8> %A, zeroinitializer;
1247   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1248        ret <8 x i8> %tmp4
1249}
1250
1251define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
1252; CHECK-LABEL: cmloz16xi8:
1253; Using registers other than v0, v1 are possible, but would be odd.
1254; LO implemented as HI, so check reversed operands.
1255; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1256; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
1257        %tmp3 = icmp ult <16 x i8> %A, zeroinitializer;
1258   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1259        ret <16 x i8> %tmp4
1260}
1261
1262define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
1263; CHECK-LABEL: cmloz4xi16:
1264; Using registers other than v0, v1 are possible, but would be odd.
1265; LO implemented as HI, so check reversed operands.
1266; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1267; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
1268        %tmp3 = icmp ult <4 x i16> %A, zeroinitializer;
1269   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1270        ret <4 x i16> %tmp4
1271}
1272
1273define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
1274; CHECK-LABEL: cmloz8xi16:
1275; Using registers other than v0, v1 are possible, but would be odd.
1276; LO implemented as HI, so check reversed operands.
1277; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1278; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
1279        %tmp3 = icmp ult <8 x i16> %A, zeroinitializer;
1280   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1281        ret <8 x i16> %tmp4
1282}
1283
1284define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
1285; CHECK-LABEL: cmloz2xi32:
1286; Using registers other than v0, v1 are possible, but would be odd.
1287; LO implemented as HI, so check reversed operands.
1288; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1289; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
1290        %tmp3 = icmp ult <2 x i32> %A, zeroinitializer;
1291   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1292        ret <2 x i32> %tmp4
1293}
1294
1295define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
1296; CHECK-LABEL: cmloz4xi32:
1297; Using registers other than v0, v1 are possible, but would be odd.
1298; LO implemented as HI, so check reversed operands.
1299; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1300; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
1301        %tmp3 = icmp ult <4 x i32> %A, zeroinitializer;
1302   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1303        ret <4 x i32> %tmp4
1304}
1305
1306define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
1307; CHECK-LABEL: cmloz2xi64:
1308; Using registers other than v0, v1 are possible, but would be odd.
1309; LO implemented as HI, so check reversed operands.
1310; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1311; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
1312        %tmp3 = icmp ult <2 x i64> %A, zeroinitializer;
1313   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1314        ret <2 x i64> %tmp4
1315}
1316
1317
1318define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
1319; CHECK-LABEL: fcmoeq2xfloat:
1320; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1321   %tmp3 = fcmp oeq <2 x float> %A, %B
1322   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1323        ret <2 x i32> %tmp4
1324}
1325
1326define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
1327; CHECK-LABEL: fcmoeq4xfloat:
1328; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1329   %tmp3 = fcmp oeq <4 x float> %A, %B
1330   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1331        ret <4 x i32> %tmp4
1332}
1333define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
1334; CHECK-LABEL: fcmoeq2xdouble:
1335; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1336   %tmp3 = fcmp oeq <2 x double> %A, %B
1337   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1338        ret <2 x i64> %tmp4
1339}
1340
1341define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
1342; CHECK-LABEL: fcmoge2xfloat:
1343; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1344   %tmp3 = fcmp oge <2 x float> %A, %B
1345   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1346        ret <2 x i32> %tmp4
1347}
1348
1349define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
1350; CHECK-LABEL: fcmoge4xfloat:
1351; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1352   %tmp3 = fcmp oge <4 x float> %A, %B
1353   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1354        ret <4 x i32> %tmp4
1355}
1356define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
1357; CHECK-LABEL: fcmoge2xdouble:
1358; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1359   %tmp3 = fcmp oge <2 x double> %A, %B
1360   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1361        ret <2 x i64> %tmp4
1362}
1363
1364define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
1365; CHECK-LABEL: fcmogt2xfloat:
1366; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1367   %tmp3 = fcmp ogt <2 x float> %A, %B
1368   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1369        ret <2 x i32> %tmp4
1370}
1371
1372define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
1373; CHECK-LABEL: fcmogt4xfloat:
1374; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1375   %tmp3 = fcmp ogt <4 x float> %A, %B
1376   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1377        ret <4 x i32> %tmp4
1378}
1379define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
1380; CHECK-LABEL: fcmogt2xdouble:
1381; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1382   %tmp3 = fcmp ogt <2 x double> %A, %B
1383   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1384        ret <2 x i64> %tmp4
1385}
1386
1387define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
1388; CHECK-LABEL: fcmole2xfloat:
1389; Using registers other than v0, v1 are possible, but would be odd.
1390; OLE implemented as OGE, so check reversed operands.
1391; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1392   %tmp3 = fcmp ole <2 x float> %A, %B
1393   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1394        ret <2 x i32> %tmp4
1395}
1396
1397define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
1398; CHECK-LABEL: fcmole4xfloat:
1399; Using registers other than v0, v1 are possible, but would be odd.
1400; OLE implemented as OGE, so check reversed operands.
1401; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1402   %tmp3 = fcmp ole <4 x float> %A, %B
1403   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1404        ret <4 x i32> %tmp4
1405}
1406define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
1407; CHECK-LABEL: fcmole2xdouble:
1408; Using registers other than v0, v1 are possible, but would be odd.
1409; OLE implemented as OGE, so check reversed operands.
1410; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1411   %tmp3 = fcmp ole <2 x double> %A, %B
1412   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1413        ret <2 x i64> %tmp4
1414}
1415
1416define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
1417; CHECK-LABEL: fcmolt2xfloat:
1418; Using registers other than v0, v1 are possible, but would be odd.
1419; OLE implemented as OGE, so check reversed operands.
1420; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1421   %tmp3 = fcmp olt <2 x float> %A, %B
1422   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1423        ret <2 x i32> %tmp4
1424}
1425
1426define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
1427; CHECK-LABEL: fcmolt4xfloat:
1428; Using registers other than v0, v1 are possible, but would be odd.
1429; OLE implemented as OGE, so check reversed operands.
1430; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1431   %tmp3 = fcmp olt <4 x float> %A, %B
1432   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1433        ret <4 x i32> %tmp4
1434}
1435define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
1436; CHECK-LABEL: fcmolt2xdouble:
1437; Using registers other than v0, v1 are possible, but would be odd.
1438; OLE implemented as OGE, so check reversed operands.
1439; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1440   %tmp3 = fcmp olt <2 x double> %A, %B
1441   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1442        ret <2 x i64> %tmp4
1443}
1444
1445define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
1446; CHECK-LABEL: fcmone2xfloat:
1447; Using registers other than v0, v1 are possible, but would be odd.
1448; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1449; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1450; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1451; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1452   %tmp3 = fcmp one <2 x float> %A, %B
1453   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1454        ret <2 x i32> %tmp4
1455}
1456
1457define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
1458; CHECK-LABEL: fcmone4xfloat:
1459; Using registers other than v0, v1 are possible, but would be odd.
1460; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1461; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1462; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1463; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1464   %tmp3 = fcmp one <4 x float> %A, %B
1465   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1466        ret <4 x i32> %tmp4
1467}
1468define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
1469; CHECK-LABEL: fcmone2xdouble:
1470; Using registers other than v0, v1 are possible, but would be odd.
1471; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1472; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1473; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1474; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1475; todo check reversed operands
1476   %tmp3 = fcmp one <2 x double> %A, %B
1477   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1478        ret <2 x i64> %tmp4
1479}
1480
1481
1482define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
1483; CHECK-LABEL: fcmord2xfloat:
1484; Using registers other than v0, v1 are possible, but would be odd.
1485; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1486; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1487; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1488; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1489   %tmp3 = fcmp ord <2 x float> %A, %B
1490   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1491        ret <2 x i32> %tmp4
1492}
1493
1494
1495define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
1496; CHECK-LABEL: fcmord4xfloat:
1497; Using registers other than v0, v1 are possible, but would be odd.
1498; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1499; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1500; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1501; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1502   %tmp3 = fcmp ord <4 x float> %A, %B
1503   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1504        ret <4 x i32> %tmp4
1505}
1506
1507define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
1508; CHECK-LABEL: fcmord2xdouble:
1509; Using registers other than v0, v1 are possible, but would be odd.
1510; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1511; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1512; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1513; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1514   %tmp3 = fcmp ord <2 x double> %A, %B
1515   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1516        ret <2 x i64> %tmp4
1517}
1518
1519
1520define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
1521; CHECK-LABEL: fcmuno2xfloat:
1522; Using registers other than v0, v1 are possible, but would be odd.
1523; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1524; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1525; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1526; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1527; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1528   %tmp3 = fcmp uno <2 x float> %A, %B
1529   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1530        ret <2 x i32> %tmp4
1531}
1532
1533define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
1534; CHECK-LABEL: fcmuno4xfloat:
1535; Using registers other than v0, v1 are possible, but would be odd.
1536; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1537; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1538; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1539; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1540; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1541   %tmp3 = fcmp uno <4 x float> %A, %B
1542   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1543        ret <4 x i32> %tmp4
1544}
1545
1546define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
1547; CHECK-LABEL: fcmuno2xdouble:
1548; Using registers other than v0, v1 are possible, but would be odd.
1549; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1550; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1551; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1552; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1553; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1554   %tmp3 = fcmp uno <2 x double> %A, %B
1555   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1556        ret <2 x i64> %tmp4
1557}
1558
1559define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
1560; CHECK-LABEL: fcmueq2xfloat:
1561; Using registers other than v0, v1 are possible, but would be odd.
1562; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1563; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1564; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1565; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1566; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1567   %tmp3 = fcmp ueq <2 x float> %A, %B
1568   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1569        ret <2 x i32> %tmp4
1570}
1571
1572define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
1573; CHECK-LABEL: fcmueq4xfloat:
1574; Using registers other than v0, v1 are possible, but would be odd.
1575; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1576; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1577; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1578; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1579; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1580   %tmp3 = fcmp ueq <4 x float> %A, %B
1581   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1582        ret <4 x i32> %tmp4
1583}
1584
1585define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
1586; CHECK-LABEL: fcmueq2xdouble:
1587; Using registers other than v0, v1 are possible, but would be odd.
1588; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1589; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1590; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1591; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1592; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1593   %tmp3 = fcmp ueq <2 x double> %A, %B
1594   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1595        ret <2 x i64> %tmp4
1596}
1597
1598define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
1599; CHECK-LABEL: fcmuge2xfloat:
1600; Using registers other than v0, v1 are possible, but would be odd.
1601; UGE = ULE with swapped operands, ULE implemented as !OGT.
1602; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1603; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1604   %tmp3 = fcmp uge <2 x float> %A, %B
1605   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1606        ret <2 x i32> %tmp4
1607}
1608
1609define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
1610; CHECK-LABEL: fcmuge4xfloat:
1611; Using registers other than v0, v1 are possible, but would be odd.
1612; UGE = ULE with swapped operands, ULE implemented as !OGT.
1613; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1614; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1615   %tmp3 = fcmp uge <4 x float> %A, %B
1616   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1617        ret <4 x i32> %tmp4
1618}
1619
1620define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
1621; CHECK-LABEL: fcmuge2xdouble:
1622; Using registers other than v0, v1 are possible, but would be odd.
1623; UGE = ULE with swapped operands, ULE implemented as !OGT.
1624; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1625; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1626   %tmp3 = fcmp uge <2 x double> %A, %B
1627   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1628        ret <2 x i64> %tmp4
1629}
1630
1631define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
1632; CHECK-LABEL: fcmugt2xfloat:
1633; Using registers other than v0, v1 are possible, but would be odd.
1634; UGT = ULT with swapped operands, ULT implemented as !OGE.
1635; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1636; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1637   %tmp3 = fcmp ugt <2 x float> %A, %B
1638   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1639        ret <2 x i32> %tmp4
1640}
1641
1642define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
1643; CHECK-LABEL: fcmugt4xfloat:
1644; Using registers other than v0, v1 are possible, but would be odd.
1645; UGT = ULT with swapped operands, ULT implemented as !OGE.
1646; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1647; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1648   %tmp3 = fcmp ugt <4 x float> %A, %B
1649   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1650        ret <4 x i32> %tmp4
1651}
1652define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
1653; CHECK-LABEL: fcmugt2xdouble:
1654; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1655; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1656   %tmp3 = fcmp ugt <2 x double> %A, %B
1657   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1658        ret <2 x i64> %tmp4
1659}
1660
1661define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
1662; CHECK-LABEL: fcmule2xfloat:
1663; Using registers other than v0, v1 are possible, but would be odd.
1664; ULE implemented as !OGT.
1665; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1666; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1667   %tmp3 = fcmp ule <2 x float> %A, %B
1668   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1669        ret <2 x i32> %tmp4
1670}
1671
1672define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
1673; CHECK-LABEL: fcmule4xfloat:
1674; Using registers other than v0, v1 are possible, but would be odd.
1675; ULE implemented as !OGT.
1676; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1677; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1678   %tmp3 = fcmp ule <4 x float> %A, %B
1679   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1680        ret <4 x i32> %tmp4
1681}
1682define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
1683; CHECK-LABEL: fcmule2xdouble:
1684; Using registers other than v0, v1 are possible, but would be odd.
1685; ULE implemented as !OGT.
1686; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1687; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1688   %tmp3 = fcmp ule <2 x double> %A, %B
1689   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1690        ret <2 x i64> %tmp4
1691}
1692
1693define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
1694; CHECK-LABEL: fcmult2xfloat:
1695; Using registers other than v0, v1 are possible, but would be odd.
1696; ULT implemented as !OGE.
1697; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1698; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1699   %tmp3 = fcmp ult <2 x float> %A, %B
1700   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1701        ret <2 x i32> %tmp4
1702}
1703
1704define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
1705; CHECK-LABEL: fcmult4xfloat:
1706; Using registers other than v0, v1 are possible, but would be odd.
1707; ULT implemented as !OGE.
1708; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1709; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1710   %tmp3 = fcmp ult <4 x float> %A, %B
1711   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1712        ret <4 x i32> %tmp4
1713}
1714define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
1715; CHECK-LABEL: fcmult2xdouble:
1716; Using registers other than v0, v1 are possible, but would be odd.
1717; ULT implemented as !OGE.
1718; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1719; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1720   %tmp3 = fcmp ult <2 x double> %A, %B
1721   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1722        ret <2 x i64> %tmp4
1723}
1724
1725define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
1726; CHECK-LABEL: fcmune2xfloat:
1727; Using registers other than v0, v1 are possible, but would be odd.
1728; UNE = !OEQ.
1729; CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s
1730; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1731   %tmp3 = fcmp une <2 x float> %A, %B
1732   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1733        ret <2 x i32> %tmp4
1734}
1735
1736define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
1737; CHECK-LABEL: fcmune4xfloat:
1738; Using registers other than v0, v1 are possible, but would be odd.
1739; UNE = !OEQ.
1740; CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s
1741; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1742   %tmp3 = fcmp une <4 x float> %A, %B
1743   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1744        ret <4 x i32> %tmp4
1745}
1746define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
1747; CHECK-LABEL: fcmune2xdouble:
1748; Using registers other than v0, v1 are possible, but would be odd.
1749; UNE = !OEQ.
1750; CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d
1751; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1752   %tmp3 = fcmp une <2 x double> %A, %B
1753   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1754        ret <2 x i64> %tmp4
1755}
1756
1757define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
1758; CHECK-LABEL: fcmoeqz2xfloat:
1759; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1760   %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
1761   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1762        ret <2 x i32> %tmp4
1763}
1764
1765define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
1766; CHECK-LABEL: fcmoeqz4xfloat:
1767; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1768   %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
1769   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1770        ret <4 x i32> %tmp4
1771}
1772define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
1773; CHECK-LABEL: fcmoeqz2xdouble:
1774; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1775   %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
1776   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1777        ret <2 x i64> %tmp4
1778}
1779
1780
1781define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
1782; CHECK-LABEL: fcmogez2xfloat:
1783; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1784   %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
1785   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1786        ret <2 x i32> %tmp4
1787}
1788
1789define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
1790; CHECK-LABEL: fcmogez4xfloat:
1791; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1792   %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
1793   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1794        ret <4 x i32> %tmp4
1795}
1796define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
1797; CHECK-LABEL: fcmogez2xdouble:
1798; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1799   %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
1800   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1801        ret <2 x i64> %tmp4
1802}
1803
1804define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
1805; CHECK-LABEL: fcmogtz2xfloat:
1806; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1807   %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
1808   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1809        ret <2 x i32> %tmp4
1810}
1811
1812define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
1813; CHECK-LABEL: fcmogtz4xfloat:
1814; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1815   %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
1816   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1817        ret <4 x i32> %tmp4
1818}
1819define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
1820; CHECK-LABEL: fcmogtz2xdouble:
1821; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1822   %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
1823   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1824        ret <2 x i64> %tmp4
1825}
1826
1827define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
1828; CHECK-LABEL: fcmoltz2xfloat:
1829; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1830   %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
1831   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1832        ret <2 x i32> %tmp4
1833}
1834
1835define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
1836; CHECK-LABEL: fcmoltz4xfloat:
1837; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1838   %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
1839   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1840        ret <4 x i32> %tmp4
1841}
1842
1843define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
1844; CHECK-LABEL: fcmoltz2xdouble:
1845; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1846   %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
1847   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1848        ret <2 x i64> %tmp4
1849}
1850
1851define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
1852; CHECK-LABEL: fcmolez2xfloat:
1853; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1854   %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
1855   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1856        ret <2 x i32> %tmp4
1857}
1858
1859define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
1860; CHECK-LABEL: fcmolez4xfloat:
1861; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1862   %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
1863   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1864        ret <4 x i32> %tmp4
1865}
1866
1867define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
1868; CHECK-LABEL: fcmolez2xdouble:
1869; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1870   %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
1871   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1872        ret <2 x i64> %tmp4
1873}
1874
1875define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
1876; CHECK-LABEL: fcmonez2xfloat:
1877; ONE with zero = OLT | OGT
1878; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1879; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1880; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1881   %tmp3 = fcmp one <2 x float> %A, zeroinitializer
1882   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1883        ret <2 x i32> %tmp4
1884}
1885
1886define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
1887; CHECK-LABEL: fcmonez4xfloat:
1888; ONE with zero = OLT | OGT
1889; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1890; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1891; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1892   %tmp3 = fcmp one <4 x float> %A, zeroinitializer
1893   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1894        ret <4 x i32> %tmp4
1895}
1896define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
1897; CHECK-LABEL: fcmonez2xdouble:
1898; ONE with zero = OLT | OGT
1899; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1900; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1901; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1902   %tmp3 = fcmp one <2 x double> %A, zeroinitializer
1903   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1904        ret <2 x i64> %tmp4
1905}
1906
1907define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
1908; CHECK-LABEL: fcmordz2xfloat:
1909; ORD with zero = OLT | OGE
1910; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1911; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1912; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1913   %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
1914   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1915        ret <2 x i32> %tmp4
1916}
1917
1918define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
1919; CHECK-LABEL: fcmordz4xfloat:
1920; ORD with zero = OLT | OGE
1921; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1922; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1923; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1924   %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
1925   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1926        ret <4 x i32> %tmp4
1927}
1928define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
1929; CHECK-LABEL: fcmordz2xdouble:
1930; ORD with zero = OLT | OGE
1931; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1932; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1933; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1934   %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
1935   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1936        ret <2 x i64> %tmp4
1937}
1938
1939define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
1940; CHECK-LABEL: fcmueqz2xfloat:
1941; UEQ with zero = !ONE = !(OLT |OGT)
1942; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1943; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1944; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1945; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1946   %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
1947   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1948        ret <2 x i32> %tmp4
1949}
1950
1951define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
1952; CHECK-LABEL: fcmueqz4xfloat:
1953; UEQ with zero = !ONE = !(OLT |OGT)
1954; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1955; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1956; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1957; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1958   %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
1959   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1960        ret <4 x i32> %tmp4
1961}
1962
1963define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
1964; CHECK-LABEL: fcmueqz2xdouble:
1965; UEQ with zero = !ONE = !(OLT |OGT)
1966; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1967; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1968; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1969; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1970   %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
1971   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1972        ret <2 x i64> %tmp4
1973}
1974
1975define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
1976; CHECK-LABEL: fcmugez2xfloat:
1977; UGE with zero = !OLT
1978; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1979; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1980   %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
1981   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1982        ret <2 x i32> %tmp4
1983}
1984
1985define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
1986; CHECK-LABEL: fcmugez4xfloat:
1987; UGE with zero = !OLT
1988; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1989; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1990   %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
1991   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1992        ret <4 x i32> %tmp4
1993}
1994define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
1995; CHECK-LABEL: fcmugez2xdouble:
1996; UGE with zero = !OLT
1997; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1998; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1999   %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
2000   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2001        ret <2 x i64> %tmp4
2002}
2003
2004define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
2005; CHECK-LABEL: fcmugtz2xfloat:
2006; UGT with zero = !OLE
2007; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2008; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2009   %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
2010   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2011        ret <2 x i32> %tmp4
2012}
2013
2014define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
2015; CHECK-LABEL: fcmugtz4xfloat:
2016; UGT with zero = !OLE
2017; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2018; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2019   %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
2020   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2021        ret <4 x i32> %tmp4
2022}
2023define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
2024; CHECK-LABEL: fcmugtz2xdouble:
2025; UGT with zero = !OLE
2026; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2027; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2028   %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
2029   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2030        ret <2 x i64> %tmp4
2031}
2032
2033define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
2034; CHECK-LABEL: fcmultz2xfloat:
2035; ULT with zero = !OGE
2036; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2037; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2038   %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
2039   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2040        ret <2 x i32> %tmp4
2041}
2042
2043define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
2044; CHECK-LABEL: fcmultz4xfloat:
2045; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2046; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2047   %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
2048   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2049        ret <4 x i32> %tmp4
2050}
2051
2052define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
2053; CHECK-LABEL: fcmultz2xdouble:
2054; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2055; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2056   %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
2057   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2058        ret <2 x i64> %tmp4
2059}
2060
2061
2062define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
2063; CHECK-LABEL: fcmulez2xfloat:
2064; ULE with zero = !OGT
2065; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2066; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2067   %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
2068   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2069        ret <2 x i32> %tmp4
2070}
2071
2072define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
2073; CHECK-LABEL: fcmulez4xfloat:
2074; ULE with zero = !OGT
2075; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2076; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2077   %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
2078   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2079        ret <4 x i32> %tmp4
2080}
2081
2082define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
2083; CHECK-LABEL: fcmulez2xdouble:
2084; ULE with zero = !OGT
2085; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2086; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2087   %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
2088   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2089        ret <2 x i64> %tmp4
2090}
2091
2092define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
2093; CHECK-LABEL: fcmunez2xfloat:
2094; UNE with zero = !OEQ with zero
2095; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2096; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2097   %tmp3 = fcmp une <2 x float> %A, zeroinitializer
2098   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2099        ret <2 x i32> %tmp4
2100}
2101
2102define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
2103; CHECK-LABEL: fcmunez4xfloat:
2104; UNE with zero = !OEQ with zero
2105; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2106; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2107   %tmp3 = fcmp une <4 x float> %A, zeroinitializer
2108   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2109        ret <4 x i32> %tmp4
2110}
2111define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
2112; CHECK-LABEL: fcmunez2xdouble:
2113; UNE with zero = !OEQ with zero
2114; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2115; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2116   %tmp3 = fcmp une <2 x double> %A, zeroinitializer
2117   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2118        ret <2 x i64> %tmp4
2119}
2120
2121
2122define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
2123; CHECK-LABEL: fcmunoz2xfloat:
2124; UNO with zero = !ORD = !(OLT | OGE)
2125; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2126; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2127; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2128; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2129   %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
2130   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2131        ret <2 x i32> %tmp4
2132}
2133
2134define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
2135; CHECK-LABEL: fcmunoz4xfloat:
2136; UNO with zero = !ORD = !(OLT | OGE)
2137; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2138; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2139; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2140; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2141   %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
2142   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2143        ret <4 x i32> %tmp4
2144}
2145
2146define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
2147; CHECK-LABEL: fcmunoz2xdouble:
2148; UNO with zero = !ORD = !(OLT | OGE)
2149; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2150; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2151; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2152; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2153   %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
2154   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2155        ret <2 x i64> %tmp4
2156
2157}
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