source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/neon-scalar-copy.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
2
3define float @test_dup_sv2S(<2 x float> %v) #0 {
4 ; CHECK-LABEL: test_dup_sv2S:
5 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
6 ; CHECK-NEXT: ret
7 %tmp1 = extractelement <2 x float> %v, i32 1
8 ret float  %tmp1
9}
10
11define float @test_dup_sv2S_0(<2 x float> %v) #0 {
12 ; CHECK-LABEL: test_dup_sv2S_0:
13 ; CHECK-NOT: dup {{[vsd][0-9]+}}
14 ; CHECK-NOT: ins {{[vsd][0-9]+}}
15 ; CHECK-NEXT: ret
16 %tmp1 = extractelement <2 x float> %v, i32 0
17 ret float  %tmp1
18}
19
20define float @test_dup_sv4S(<4 x float> %v) #0 {
21 ; CHECK-LABEL: test_dup_sv4S:
22 ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
23 ; CHECK-NEXT: ret
24 %tmp1 = extractelement <4 x float> %v, i32 1
25 ret float  %tmp1
26}
27
28define float @test_dup_sv4S_0(<4 x float> %v) #0 {
29 ; CHECK-LABEL: test_dup_sv4S_0:
30 ; CHECK-NOT: dup {{[vsd][0-9]+}}
31 ; CHECK-NOT: ins {{[vsd][0-9]+}}
32 ; CHECK-NEXT: ret
33 %tmp1 = extractelement <4 x float> %v, i32 0
34 ret float  %tmp1
35}
36
37define double @test_dup_dvD(<1 x double> %v) #0 {
38 ; CHECK-LABEL: test_dup_dvD:
39 ; CHECK-NOT: dup {{[vsd][0-9]+}}
40 ; CHECK-NOT: ins {{[vsd][0-9]+}}
41 ; CHECK-NEXT: ret
42 %tmp1 = extractelement <1 x double> %v, i32 0
43 ret double  %tmp1
44}
45
46define double @test_dup_dv2D(<2 x double> %v) #0 {
47 ; CHECK-LABEL: test_dup_dv2D:
48 ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
49 ; CHECK-NEXT: ret
50 %tmp1 = extractelement <2 x double> %v, i32 1
51 ret double  %tmp1
52}
53
54define double @test_dup_dv2D_0(<2 x double> %v) #0 {
55 ; CHECK-LABEL: test_dup_dv2D_0:
56 ; CHECK-NOT: dup {{[vsd][0-9]+}}
57 ; CHECK-NOT: ins {{[vsd][0-9]+}}
58 ; CHECK-NEXT: ret
59 %tmp1 = extractelement <2 x double> %v, i32 0
60 ret double  %tmp1
61}
62
63define half @test_dup_hv8H(<8 x half> %v) #0 {
64 ; CHECK-LABEL: test_dup_hv8H:
65 ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
66 ; CHECK-NEXT: ret
67 %tmp1 = extractelement <8 x half> %v, i32 1
68 ret half  %tmp1
69}
70
71define half @test_dup_hv8H_0(<8 x half> %v) #0 {
72 ; CHECK-LABEL: test_dup_hv8H_0:
73 ; CHECK-NOT: dup {{[vsdh][0-9]+}}
74 ; CHECK-NOT: ins {{[vsdh][0-9]+}}
75 ; CHECK-NEXT: ret
76 %tmp1 = extractelement <8 x half> %v, i32 0
77 ret half  %tmp1
78}
79
80define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
81 ; CHECK-LABEL: test_vector_dup_bv16B:
82 ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
83 ; CHECK-NEXT: fmov s0, [[W]]
84 ; CHECK-NEXT: ret
85 %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
86 ret <1 x i8> %shuffle.i
87}
88
89define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
90 ; CHECK-LABEL: test_vector_dup_bv8B:
91 ; CHECK-NEXT: dup v0.8b, v0.b[7]
92 ; CHECK-NEXT: ret
93 %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
94 ret <1 x i8> %shuffle.i
95}
96
97define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
98 ; CHECK-LABEL: test_vector_dup_hv8H:
99 ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
100 ; CHECK-NEXT: fmov s0, [[W]]
101 ; CHECK-NEXT: ret
102 %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
103 ret <1 x i16> %shuffle.i
104}
105
106define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
107 ; CHECK-LABEL: test_vector_dup_hv4H:
108 ; CHECK-NEXT: dup v0.4h, v0.h[3]
109 ; CHECK-NEXT: ret
110 %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
111 ret <1 x i16> %shuffle.i
112}
113
114define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
115 ; CHECK-LABEL: test_vector_dup_sv4S:
116 ; CHECK-NEXT: mov  [[W:w[0-9]+]], v0.s[3]
117 ; CHECK-NEXT: fmov s0, [[W]]
118 ; CHECK-NEXT: ret
119 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
120 ret <1 x i32> %shuffle
121}
122
123define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
124 ; CHECK-LABEL: test_vector_dup_sv2S:
125 ; CHECK-NEXT: dup v0.2s, v0.s[1]
126 ; CHECK-NEXT: ret
127 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
128 ret <1 x i32> %shuffle
129}
130
131define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
132 ; CHECK-LABEL: test_vector_dup_dv2D:
133 ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
134 ; CHECK-NEXT: ret
135 %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
136 ret <1 x i64> %shuffle.i
137}
138
139define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
140  ; CHECK-LABEL: test_vector_copy_dup_dv2D:
141  ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
142  ; CHECK-NEXT: ret
143  %vget_lane = extractelement <2 x i64> %c, i32 1
144  %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
145  ret <1 x i64> %vset_lane
146}
147
148; Undefined behaviour, so we really don't care what actually gets emitted, just
149; as long as we don't crash (since it could be dynamically unreachable).
150define i32 @test_out_of_range_extract(<4 x i32> %vec) {
151; CHECK-LABEL: test_out_of_range_extract:
152; CHECK: ret
153  %elt = extractelement <4 x i32> %vec, i32 4
154  ret i32 %elt
155}
156
157; Undefined behaviour, so we really don't care what actually gets emitted, just
158; as long as we don't crash (since it could be dynamically unreachable).
159define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
160; CHECK-LABEL: test_out_of_range_insert:
161; CHECK: ret
162  insertelement <4 x i32> %vec, i32 %elt, i32 4
163  ret void
164}
165
166attributes #0 = { nounwind }
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