source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AArch64/neon-truncStore-extLoad.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

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Line 
1; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2
3; A vector TruncStore can not be selected.
4; Test a trunc IR and a vector store IR can be selected correctly.
5define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
6; CHECK-LABEL: truncStore.v2i64:
7; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
8; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
9  %b = trunc <2 x i64> %a to <2 x i32>
10  store <2 x i32> %b, <2 x i32>* %result
11  ret void
12}
13
14define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
15; CHECK-LABEL: truncStore.v4i32:
16; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
17; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
18  %b = trunc <4 x i32> %a to <4 x i16>
19  store <4 x i16> %b, <4 x i16>* %result
20  ret void
21}
22
23define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
24; CHECK-LABEL: truncStore.v8i16:
25; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
26; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
27  %b = trunc <8 x i16> %a to <8 x i8>
28  store <8 x i8> %b, <8 x i8>* %result
29  ret void
30}
31
32; A vector LoadExt can not be selected.
33; Test a vector load IR and a sext/zext IR can be selected correctly.
34define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
35; CHECK-LABEL: loadSExt.v4i8:
36; CHECK: ldrsb
37  %a = load <4 x i8>, <4 x i8>* %ref
38  %conv = sext <4 x i8> %a to <4 x i32>
39  ret <4 x i32> %conv
40}
41
42define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
43; CHECK-LABEL: loadZExt.v4i8:
44; CHECK: ldrb
45  %a = load <4 x i8>, <4 x i8>* %ref
46  %conv = zext <4 x i8> %a to <4 x i32>
47  ret <4 x i32> %conv
48}
49
50define i32 @loadExt.i32(<4 x i8>* %ref) {
51; CHECK-LABEL: loadExt.i32:
52; CHECK: ldrb
53  %a = load <4 x i8>, <4 x i8>* %ref
54  %vecext = extractelement <4 x i8> %a, i32 0
55  %conv = zext i8 %vecext to i32
56  ret i32 %conv
57}
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