source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/commute-shifts.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.3 KB
Line 
1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; GCN-LABEL: {{^}}main:
5; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
6; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1
7
8define void @main() #0 {
9main_body:
10  %0 = fptosi float undef to i32
11  %1 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> undef, <32 x i8> undef, i32 2)
12  %2 = extractelement <4 x i32> %1, i32 0
13  %3 = and i32 %0, 7
14  %4 = shl i32 1, %3
15  %5 = and i32 %2, %4
16  %6 = icmp eq i32 %5, 0
17  %.10 = select i1 %6, float 0.000000e+00, float undef
18  %7 = call i32 @llvm.SI.packf16(float undef, float %.10)
19  %8 = bitcast i32 %7 to float
20  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %8, float undef, float %8)
21  ret void
22}
23
24; Function Attrs: nounwind readnone
25declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1
26
27; Function Attrs: nounwind readnone
28declare i32 @llvm.SI.packf16(float, float) #1
29
30declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
31
32attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" }
33attributes #1 = { nounwind readnone }
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