source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 3.0 KB
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1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
4
5declare float @llvm.fabs.f32(float) #1
6declare float @llvm.floor.f32(float) #1
7
8; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
9; SI-SAFE-NOT: v_cvt_flr_i32_f32
10; SI-NOT: add
11; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
12; SI: s_endpgm
13define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
14  %floor = call float @llvm.floor.f32(float %x) #1
15  %cvt = fptosi float %floor to i32
16  store i32 %cvt, i32 addrspace(1)* %out
17  ret void
18}
19
20; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
21; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
22; SI-SAFE-NOT: v_cvt_flr_i32_f32
23; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
24; SI: s_endpgm
25define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
26  %fadd = fadd float %x, 1.0
27  %floor = call float @llvm.floor.f32(float %fadd) #1
28  %cvt = fptosi float %floor to i32
29  store i32 %cvt, i32 addrspace(1)* %out
30  ret void
31}
32
33; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
34; SI-NOT: add
35; SI-SAFE-NOT: v_cvt_flr_i32_f32
36; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
37; SI: s_endpgm
38define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
39  %x.fabs = call float @llvm.fabs.f32(float %x) #1
40  %floor = call float @llvm.floor.f32(float %x.fabs) #1
41  %cvt = fptosi float %floor to i32
42  store i32 %cvt, i32 addrspace(1)* %out
43  ret void
44}
45
46; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
47; SI-NOT: add
48; SI-SAFE-NOT: v_cvt_flr_i32_f32
49; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
50; SI: s_endpgm
51define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
52  %x.fneg = fsub float -0.000000e+00, %x
53  %floor = call float @llvm.floor.f32(float %x.fneg) #1
54  %cvt = fptosi float %floor to i32
55  store i32 %cvt, i32 addrspace(1)* %out
56  ret void
57}
58
59; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
60; SI-NOT: add
61; SI-SAFE-NOT: v_cvt_flr_i32_f32
62; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
63; SI: s_endpgm
64define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
65  %x.fabs = call float @llvm.fabs.f32(float %x) #1
66  %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
67  %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
68  %cvt = fptosi float %floor to i32
69  store i32 %cvt, i32 addrspace(1)* %out
70  ret void
71}
72
73; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:
74; SI-NOT: v_cvt_flr_i32_f32
75; SI: v_floor_f32
76; SI: v_cvt_u32_f32_e32
77; SI: s_endpgm
78define void @no_cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
79  %floor = call float @llvm.floor.f32(float %x) #1
80  %cvt = fptoui float %floor to i32
81  store i32 %cvt, i32 addrspace(1)* %out
82  ret void
83}
84
85attributes #0 = { nounwind }
86attributes #1 = { nounwind readnone }
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