source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/ds_read2.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefix=SI %s
2
3; FIXME: We don't get cases where the address was an SGPR because we
4; get a copy to the address register for each one.
5
6@lds = addrspace(3) global [512 x float] undef, align 4
7@lds.f64 = addrspace(3) global [512 x double] undef, align 8
8
9; SI-LABEL: @simple_read2_f32
10; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:8
11; SI: s_waitcnt lgkmcnt(0)
12; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
13; SI: buffer_store_dword [[RESULT]]
14; SI: s_endpgm
15define void @simple_read2_f32(float addrspace(1)* %out) #0 {
16  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
17  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
18  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
19  %add.x = add nsw i32 %x.i, 8
20  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
21  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
22  %sum = fadd float %val0, %val1
23  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
24  store float %sum, float addrspace(1)* %out.gep, align 4
25  ret void
26}
27
28; SI-LABEL: @simple_read2_f32_max_offset
29; SI: ds_read2_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:255
30; SI: s_waitcnt lgkmcnt(0)
31; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]]
32; SI: buffer_store_dword [[RESULT]]
33; SI: s_endpgm
34define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 {
35  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
36  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
37  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
38  %add.x = add nsw i32 %x.i, 255
39  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
40  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
41  %sum = fadd float %val0, %val1
42  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
43  store float %sum, float addrspace(1)* %out.gep, align 4
44  ret void
45}
46
47; SI-LABEL: @simple_read2_f32_too_far
48; SI-NOT ds_read2_b32
49; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
50; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028
51; SI: s_endpgm
52define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 {
53  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
54  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
55  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
56  %add.x = add nsw i32 %x.i, 257
57  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
58  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
59  %sum = fadd float %val0, %val1
60  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
61  store float %sum, float addrspace(1)* %out.gep, align 4
62  ret void
63}
64
65; SI-LABEL: @simple_read2_f32_x2
66; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
67; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
68; SI: s_endpgm
69define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 {
70  %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
71  %idx.0 = add nsw i32 %tid.x, 0
72  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
73  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
74
75  %idx.1 = add nsw i32 %tid.x, 8
76  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
77  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
78  %sum.0 = fadd float %val0, %val1
79
80  %idx.2 = add nsw i32 %tid.x, 11
81  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
82  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
83
84  %idx.3 = add nsw i32 %tid.x, 27
85  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
86  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
87  %sum.1 = fadd float %val2, %val3
88
89  %sum = fadd float %sum.0, %sum.1
90  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
91  store float %sum, float addrspace(1)* %out.gep, align 4
92  ret void
93}
94
95; Make sure there is an instruction between the two sets of reads.
96; SI-LABEL: @simple_read2_f32_x2_barrier
97; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset1:8
98; SI: s_barrier
99; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
100; SI: s_endpgm
101define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 {
102  %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
103  %idx.0 = add nsw i32 %tid.x, 0
104  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
105  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
106
107  %idx.1 = add nsw i32 %tid.x, 8
108  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
109  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
110  %sum.0 = fadd float %val0, %val1
111
112  call void @llvm.AMDGPU.barrier.local() #2
113
114  %idx.2 = add nsw i32 %tid.x, 11
115  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
116  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
117
118  %idx.3 = add nsw i32 %tid.x, 27
119  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
120  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
121  %sum.1 = fadd float %val2, %val3
122
123  %sum = fadd float %sum.0, %sum.1
124  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
125  store float %sum, float addrspace(1)* %out.gep, align 4
126  ret void
127}
128
129; For some reason adding something to the base address for the first
130; element results in only folding the inner pair.
131
132; SI-LABEL: @simple_read2_f32_x2_nonzero_base
133; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:2 offset1:8
134; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
135; SI: s_endpgm
136define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 {
137  %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
138  %idx.0 = add nsw i32 %tid.x, 2
139  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0
140  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
141
142  %idx.1 = add nsw i32 %tid.x, 8
143  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1
144  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
145  %sum.0 = fadd float %val0, %val1
146
147  %idx.2 = add nsw i32 %tid.x, 11
148  %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2
149  %val2 = load float, float addrspace(3)* %arrayidx2, align 4
150
151  %idx.3 = add nsw i32 %tid.x, 27
152  %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3
153  %val3 = load float, float addrspace(3)* %arrayidx3, align 4
154  %sum.1 = fadd float %val2, %val3
155
156  %sum = fadd float %sum.0, %sum.1
157  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %idx.0
158  store float %sum, float addrspace(1)* %out.gep, align 4
159  ret void
160}
161
162; Be careful of vectors of pointers. We don't know if the 2 pointers
163; in the vectors are really the same base, so this is not safe to
164; merge.
165; Base pointers come from different subregister of same super
166; register. We can't safely merge this.
167
168; SI-LABEL: @read2_ptr_is_subreg_arg_f32
169; SI-NOT: ds_read2_b32
170; SI: ds_read_b32
171; SI: ds_read_b32
172; SI: s_endpgm
173define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 {
174  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
175  %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
176  %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
177  %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
178  %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
179  %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
180  %val0 = load float, float addrspace(3)* %gep.0, align 4
181  %val1 = load float, float addrspace(3)* %gep.1, align 4
182  %add.x = add nsw i32 %x.i, 8
183  %sum = fadd float %val0, %val1
184  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
185  store float %sum, float addrspace(1)* %out.gep, align 4
186  ret void
187}
188
189; Apply a constant scalar offset after the pointer vector extract.  We
190; are rejecting merges that have the same, constant 0 offset, so make
191; sure we are really rejecting it because of the different
192; subregisters.
193
194; SI-LABEL: @read2_ptr_is_subreg_arg_offset_f32
195; SI-NOT: ds_read2_b32
196; SI: ds_read_b32
197; SI: ds_read_b32
198; SI: s_endpgm
199define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 {
200  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
201  %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
202  %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
203  %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1
204  %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
205  %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
206
207  ; Apply an additional offset after the vector that will be more obviously folded.
208  %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8
209
210  %val0 = load float, float addrspace(3)* %gep.0, align 4
211  %val1 = load float, float addrspace(3)* %gep.1.offset, align 4
212  %add.x = add nsw i32 %x.i, 8
213  %sum = fadd float %val0, %val1
214  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
215  store float %sum, float addrspace(1)* %out.gep, align 4
216  ret void
217}
218
219; SI-LABEL: {{^}}read2_ptr_is_subreg_f32:
220; SI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:8{{$}}
221; SI: s_endpgm
222define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 {
223  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
224  %ptr.0 = insertelement <2 x [512 x float] addrspace(3)*> undef, [512 x float] addrspace(3)* @lds, i32 0
225  %ptr.1 = insertelement <2 x [512 x float] addrspace(3)*> %ptr.0, [512 x float] addrspace(3)* @lds, i32 1
226  %x.i.v.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
227  %x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1
228  %idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>
229  %gep = getelementptr inbounds [512 x float], <2 x [512 x float] addrspace(3)*> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx
230  %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0
231  %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1
232  %val0 = load float, float addrspace(3)* %gep.0, align 4
233  %val1 = load float, float addrspace(3)* %gep.1, align 4
234  %add.x = add nsw i32 %x.i, 8
235  %sum = fadd float %val0, %val1
236  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
237  store float %sum, float addrspace(1)* %out.gep, align 4
238  ret void
239}
240
241; SI-LABEL: @simple_read2_f32_volatile_0
242; SI-NOT ds_read2_b32
243; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
244; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
245; SI: s_endpgm
246define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 {
247  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
248  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
249  %val0 = load volatile float, float addrspace(3)* %arrayidx0, align 4
250  %add.x = add nsw i32 %x.i, 8
251  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
252  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
253  %sum = fadd float %val0, %val1
254  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
255  store float %sum, float addrspace(1)* %out.gep, align 4
256  ret void
257}
258
259; SI-LABEL: @simple_read2_f32_volatile_1
260; SI-NOT ds_read2_b32
261; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}
262; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32
263; SI: s_endpgm
264define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 {
265  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
266  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
267  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
268  %add.x = add nsw i32 %x.i, 8
269  %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
270  %val1 = load volatile float, float addrspace(3)* %arrayidx1, align 4
271  %sum = fadd float %val0, %val1
272  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
273  store float %sum, float addrspace(1)* %out.gep, align 4
274  ret void
275}
276
277; Can't fold since not correctly aligned.
278; XXX: This isn't really testing anything useful now. I think CI
279; allows unaligned LDS accesses, which would be a problem here.
280; SI-LABEL: @unaligned_read2_f32
281; SI-NOT: ds_read2_b32
282; SI: s_endpgm
283define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
284  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
285  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
286  %val0 = load float, float addrspace(3)* %arrayidx0, align 1
287  %add.x = add nsw i32 %x.i, 8
288  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
289  %val1 = load float, float addrspace(3)* %arrayidx1, align 1
290  %sum = fadd float %val0, %val1
291  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
292  store float %sum, float addrspace(1)* %out.gep, align 4
293  ret void
294}
295
296; SI-LABEL: @misaligned_2_simple_read2_f32
297; SI-NOT: ds_read2_b32
298; SI: s_endpgm
299define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
300  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
301  %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
302  %val0 = load float, float addrspace(3)* %arrayidx0, align 2
303  %add.x = add nsw i32 %x.i, 8
304  %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
305  %val1 = load float, float addrspace(3)* %arrayidx1, align 2
306  %sum = fadd float %val0, %val1
307  %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
308  store float %sum, float addrspace(1)* %out.gep, align 4
309  ret void
310}
311
312; SI-LABEL: @simple_read2_f64
313; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}}
314; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
315; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}
316; SI: buffer_store_dwordx2 [[RESULT]]
317; SI: s_endpgm
318define void @simple_read2_f64(double addrspace(1)* %out) #0 {
319  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
320  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
321  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
322  %add.x = add nsw i32 %x.i, 8
323  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
324  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
325  %sum = fadd double %val0, %val1
326  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
327  store double %sum, double addrspace(1)* %out.gep, align 8
328  ret void
329}
330
331; SI-LABEL: @simple_read2_f64_max_offset
332; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:255
333; SI: s_endpgm
334define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 {
335  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
336  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
337  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
338  %add.x = add nsw i32 %x.i, 255
339  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
340  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
341  %sum = fadd double %val0, %val1
342  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
343  store double %sum, double addrspace(1)* %out.gep, align 8
344  ret void
345}
346
347; SI-LABEL: @simple_read2_f64_too_far
348; SI-NOT ds_read2_b64
349; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
350; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:2056
351; SI: s_endpgm
352define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 {
353  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
354  %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i
355  %val0 = load double, double addrspace(3)* %arrayidx0, align 8
356  %add.x = add nsw i32 %x.i, 257
357  %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x
358  %val1 = load double, double addrspace(3)* %arrayidx1, align 8
359  %sum = fadd double %val0, %val1
360  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
361  store double %sum, double addrspace(1)* %out.gep, align 8
362  ret void
363}
364
365; Alignment only 4
366; SI-LABEL: @misaligned_read2_f64
367; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:1
368; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15
369; SI: s_endpgm
370define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 {
371  %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
372  %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i
373  %val0 = load double, double addrspace(3)* %arrayidx0, align 4
374  %add.x = add nsw i32 %x.i, 7
375  %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x
376  %val1 = load double, double addrspace(3)* %arrayidx1, align 4
377  %sum = fadd double %val0, %val1
378  %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i32 %x.i
379  store double %sum, double addrspace(1)* %out.gep, align 4
380  ret void
381}
382
383@foo = addrspace(3) global [4 x i32] undef, align 4
384
385; SI-LABEL: @load_constant_adjacent_offsets
386; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
387; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
388define void @load_constant_adjacent_offsets(i32 addrspace(1)* %out) {
389  %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
390  %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4
391  %sum = add i32 %val0, %val1
392  store i32 %sum, i32 addrspace(1)* %out, align 4
393  ret void
394}
395
396; SI-LABEL: @load_constant_disjoint_offsets
397; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
398; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:2
399define void @load_constant_disjoint_offsets(i32 addrspace(1)* %out) {
400  %val0 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4
401  %val1 = load i32, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4
402  %sum = add i32 %val0, %val1
403  store i32 %sum, i32 addrspace(1)* %out, align 4
404  ret void
405}
406
407@bar = addrspace(3) global [4 x i64] undef, align 4
408
409; SI-LABEL: @load_misaligned64_constant_offsets
410; SI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
411; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset1:1
412; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3
413define void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
414  %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
415  %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
416  %sum = add i64 %val0, %val1
417  store i64 %sum, i64 addrspace(1)* %out, align 8
418  ret void
419}
420
421@bar.large = addrspace(3) global [4096 x i64] undef, align 4
422
423; SI-LABEL: @load_misaligned64_constant_large_offsets
424; SI-DAG: v_mov_b32_e32 [[BASE0:v[0-9]+]], 0x7ff8{{$}}
425; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000
426; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE0]] offset1:1
427; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset1:1
428; SI: s_endpgm
429define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) {
430  %val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4
431  %val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4
432  %sum = add i64 %val0, %val1
433  store i64 %sum, i64 addrspace(1)* %out, align 8
434  ret void
435}
436
437@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
438@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
439
440define void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb) #0 {
441  %x.i = tail call i32 @llvm.r600.read.tgid.x() #1
442  %y.i = tail call i32 @llvm.r600.read.tidig.y() #1
443  %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i
444  %tmp16 = load float, float addrspace(3)* %arrayidx44, align 4
445  %add47 = add nsw i32 %x.i, 1
446  %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47
447  %tmp17 = load float, float addrspace(3)* %arrayidx48, align 4
448  %add51 = add nsw i32 %x.i, 16
449  %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51
450  %tmp18 = load float, float addrspace(3)* %arrayidx52, align 4
451  %add55 = add nsw i32 %x.i, 17
452  %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55
453  %tmp19 = load float, float addrspace(3)* %arrayidx56, align 4
454  %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i
455  %tmp20 = load float, float addrspace(3)* %arrayidx60, align 4
456  %add63 = add nsw i32 %y.i, 1
457  %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63
458  %tmp21 = load float, float addrspace(3)* %arrayidx64, align 4
459  %add67 = add nsw i32 %y.i, 32
460  %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67
461  %tmp22 = load float, float addrspace(3)* %arrayidx68, align 4
462  %add71 = add nsw i32 %y.i, 33
463  %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71
464  %tmp23 = load float, float addrspace(3)* %arrayidx72, align 4
465  %add75 = add nsw i32 %y.i, 64
466  %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75
467  %tmp24 = load float, float addrspace(3)* %arrayidx76, align 4
468  %add79 = add nsw i32 %y.i, 65
469  %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79
470  %tmp25 = load float, float addrspace(3)* %arrayidx80, align 4
471  %sum.0 = fadd float %tmp16, %tmp17
472  %sum.1 = fadd float %sum.0, %tmp18
473  %sum.2 = fadd float %sum.1, %tmp19
474  %sum.3 = fadd float %sum.2, %tmp20
475  %sum.4 = fadd float %sum.3, %tmp21
476  %sum.5 = fadd float %sum.4, %tmp22
477  %sum.6 = fadd float %sum.5, %tmp23
478  %sum.7 = fadd float %sum.6, %tmp24
479  %sum.8 = fadd float %sum.7, %tmp25
480  store float %sum.8, float addrspace(1)* %C, align 4
481  ret void
482}
483
484define void @misaligned_read2_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(3)* %in) #0 {
485  %load = load <2 x i32>, <2 x i32> addrspace(3)* %in, align 4
486  store <2 x i32> %load, <2 x i32> addrspace(1)* %out, align 8
487  ret void
488}
489
490define void @misaligned_read2_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) #0 {
491  %load = load i64, i64 addrspace(3)* %in, align 4
492  store i64 %load, i64 addrspace(1)* %out, align 8
493  ret void
494}
495
496; Function Attrs: nounwind readnone
497declare i32 @llvm.r600.read.tgid.x() #1
498
499; Function Attrs: nounwind readnone
500declare i32 @llvm.r600.read.tgid.y() #1
501
502; Function Attrs: nounwind readnone
503declare i32 @llvm.r600.read.tidig.x() #1
504
505; Function Attrs: nounwind readnone
506declare i32 @llvm.r600.read.tidig.y() #1
507
508; Function Attrs: convergent nounwind
509declare void @llvm.AMDGPU.barrier.local() #2
510
511attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
512attributes #1 = { nounwind readnone }
513attributes #2 = { convergent nounwind }
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