source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/fcmp.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.1 KB
Line 
1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3; CHECK: {{^}}fcmp_sext:
4; CHECK: SETE_DX10  T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
5
6define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) {
7entry:
8  %0 = load float, float addrspace(1)* %in
9  %arrayidx1 = getelementptr inbounds float, float addrspace(1)* %in, i32 1
10  %1 = load float, float addrspace(1)* %arrayidx1
11  %cmp = fcmp oeq float %0, %1
12  %sext = sext i1 %cmp to i32
13  store i32 %sext, i32 addrspace(1)* %out
14  ret void
15}
16
17; This test checks that a setcc node with f32 operands is lowered to a
18; SET*_DX10 instruction.  Previously we were lowering this to:
19; SET* + FP_TO_SINT
20
21; CHECK: {{^}}fcmp_br:
22; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
23; CHECK-NEXT: {{[0-9]+\(5.0}}
24
25define void @fcmp_br(i32 addrspace(1)* %out, float %in) {
26entry:
27  %0 = fcmp oeq float %in, 5.0
28  br i1 %0, label %IF, label %ENDIF
29
30IF:
31  %1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
32  store i32 0, i32 addrspace(1)* %1
33  br label %ENDIF
34
35ENDIF:
36  store i32 0, i32 addrspace(1)* %out
37  ret void
38}
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