source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/fp16_to_fp.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.3 KB
Line 
1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
5declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
6
7; SI-LABEL: {{^}}test_convert_fp16_to_fp32:
8; SI: buffer_load_ushort [[VAL:v[0-9]+]]
9; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
10; SI: buffer_store_dword [[RESULT]]
11define void @test_convert_fp16_to_fp32(float addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
12  %val = load i16, i16 addrspace(1)* %in, align 2
13  %cvt = call float @llvm.convert.from.fp16.f32(i16 %val) nounwind readnone
14  store float %cvt, float addrspace(1)* %out, align 4
15  ret void
16}
17
18
19; SI-LABEL: {{^}}test_convert_fp16_to_fp64:
20; SI: buffer_load_ushort [[VAL:v[0-9]+]]
21; SI: v_cvt_f32_f16_e32 [[RESULT32:v[0-9]+]], [[VAL]]
22; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
23; SI: buffer_store_dwordx2 [[RESULT]]
24define void @test_convert_fp16_to_fp64(double addrspace(1)* noalias %out, i16 addrspace(1)* noalias %in) nounwind {
25  %val = load i16, i16 addrspace(1)* %in, align 2
26  %cvt = call double @llvm.convert.from.fp16.f64(i16 %val) nounwind readnone
27  store double %cvt, double addrspace(1)* %out, align 4
28  ret void
29}
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