source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

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Line 
1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
3
4declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone
5declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone
6
7; GCN-LABEL: {{^}}test_div_fixup_f32:
8; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
9; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
10; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
11; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
12; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
13; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
14; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
15; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
16; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]]
17; GCN: buffer_store_dword [[RESULT]],
18; GCN: s_endpgm
19define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
20  %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone
21  store float %result, float addrspace(1)* %out, align 4
22  ret void
23}
24
25; GCN-LABEL: {{^}}test_div_fixup_f64:
26; GCN: v_div_fixup_f64
27define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind {
28  %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone
29  store double %result, double addrspace(1)* %out, align 8
30  ret void
31}
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