source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/operand-folding.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 3.5 KB
Line 
1; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
2
3; CHECK-LABEL: {{^}}fold_sgpr:
4; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s
5define void @fold_sgpr(i32 addrspace(1)* %out, i32 %fold) {
6entry:
7  %tmp0 = icmp ne i32 %fold, 0
8  br i1 %tmp0, label %if, label %endif
9
10if:
11  %id = call i32 @llvm.r600.read.tidig.x()
12  %offset = add i32 %fold, %id
13  %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
14  store i32 0, i32 addrspace(1)* %tmp1
15  br label %endif
16
17endif:
18  ret void
19}
20
21; CHECK-LABEL: {{^}}fold_imm:
22; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
23define void @fold_imm(i32 addrspace(1)* %out, i32 %cmp) {
24entry:
25  %fold = add i32 3, 2
26  %tmp0 = icmp ne i32 %cmp, 0
27  br i1 %tmp0, label %if, label %endif
28
29if:
30  %id = call i32 @llvm.r600.read.tidig.x()
31  %val = or i32 %id, %fold
32  store i32 %val, i32 addrspace(1)* %out
33  br label %endif
34
35endif:
36  ret void
37}
38
39; CHECK-LABEL: {{^}}fold_64bit_constant_add:
40; CHECK-NOT: s_mov_b64
41; FIXME: It would be better if we could use v_add here and drop the extra
42; v_mov_b32 instructions.
43; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
44; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
45; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
46; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
47; CHECK: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}},
48
49define void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) {
50entry:
51  %tmp0 = add i64 %val, 1
52  store i64 %tmp0, i64 addrspace(1)* %out
53  ret void
54}
55
56; Inline constants should always be folded.
57
58; CHECK-LABEL: {{^}}vector_inline:
59; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
60; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
61; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
62; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
63
64define void @vector_inline(<4 x i32> addrspace(1)* %out) {
65entry:
66  %tmp0 = call i32 @llvm.r600.read.tidig.x()
67  %tmp1 = add i32 %tmp0, 1
68  %tmp2 = add i32 %tmp0, 2
69  %tmp3 = add i32 %tmp0, 3
70  %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
71  %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
72  %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
73  %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
74  %tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
75  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
76  ret void
77}
78
79; Immediates with one use should be folded
80; CHECK-LABEL: {{^}}imm_one_use:
81; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}
82
83define void @imm_one_use(i32 addrspace(1)* %out) {
84entry:
85  %tmp0 = call i32 @llvm.r600.read.tidig.x()
86  %tmp1 = xor i32 %tmp0, 100
87  store i32 %tmp1, i32 addrspace(1)* %out
88  ret void
89}
90; CHECK-LABEL: {{^}}vector_imm:
91; CHECK: s_movk_i32 [[IMM:s[0-9]+]], 0x64
92; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
93; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
94; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
95; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
96
97define void @vector_imm(<4 x i32> addrspace(1)* %out) {
98entry:
99  %tmp0 = call i32 @llvm.r600.read.tidig.x()
100  %tmp1 = add i32 %tmp0, 1
101  %tmp2 = add i32 %tmp0, 2
102  %tmp3 = add i32 %tmp0, 3
103  %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
104  %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
105  %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
106  %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
107  %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
108  store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
109  ret void
110}
111
112declare i32 @llvm.r600.read.tidig.x() #0
113attributes #0 = { readnone }
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