source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/rv7x0_count3.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 2.0 KB
Line 
1; RUN: llc < %s -march=r600 -show-mc-encoding  -mcpu=rv710 | FileCheck %s
2
3; CHECK: TEX 9 @6 ;  encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
4
5define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6   %1 = extractelement <4 x float> %reg1, i32 0
7   %2 = extractelement <4 x float> %reg1, i32 1
8   %3 = extractelement <4 x float> %reg1, i32 2
9   %4 = extractelement <4 x float> %reg1, i32 3
10   %5 = insertelement <4 x float> undef, float %1, i32 0
11   %6 = insertelement <4 x float> %5, float %2, i32 1
12   %7 = insertelement <4 x float> %6, float %3, i32 2
13   %8 = insertelement <4 x float> %7, float %4, i32 3
14   %9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
15   %10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 1, i32 0, i32 1)
16   %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 2, i32 0, i32 1)
17   %12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 3, i32 0, i32 1)
18   %13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 4, i32 0, i32 1)
19   %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 5, i32 0, i32 1)
20   %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 6, i32 0, i32 1)
21   %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 7, i32 0, i32 1)
22   %17 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 8, i32 0, i32 1)
23   %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 9, i32 0, i32 1)
24   %19 = fadd <4 x float> %9, %10
25   %20 = fadd <4 x float> %19, %11
26   %21 = fadd <4 x float> %20, %12
27   %22 = fadd <4 x float> %21, %13
28   %23 = fadd <4 x float> %22, %14
29   %24 = fadd <4 x float> %23, %15
30   %25 = fadd <4 x float> %24, %16
31   %26 = fadd <4 x float> %25, %17
32   %27 = fadd <4 x float> %26, %18
33   call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2)
34   ret void
35}
36
37declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
38
39declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
40
41attributes #0 = { "ShaderType"="1" }
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