source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/schedule-global-loads.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.7 KB
Line 
1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
2
3
4declare i32 @llvm.r600.read.tidig.x() #1
5
6; FIXME: This currently doesn't do a great job of clustering the
7; loads, which end up with extra moves between them. Right now, it
8; seems the only things areLoadsFromSameBasePtr is accomplishing is
9; ordering the loads so that the lower address loads come first.
10
11; FUNC-LABEL: {{^}}cluster_global_arg_loads:
12; SI-DAG: buffer_load_dword [[REG0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
13; SI-DAG: buffer_load_dword [[REG1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4
14; SI: buffer_store_dword [[REG0]]
15; SI: buffer_store_dword [[REG1]]
16define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 {
17  %load0 = load i32, i32 addrspace(1)* %ptr, align 4
18  %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 1
19  %load1 = load i32, i32 addrspace(1)* %gep, align 4
20  store i32 %load0, i32 addrspace(1)* %out0, align 4
21  store i32 %load1, i32 addrspace(1)* %out1, align 4
22  ret void
23}
24
25; Test for a crach in SIInstrInfo::areLoadsFromSameBasePtr() when checking
26; an MUBUF load which does not have a vaddr operand.
27; FUNC-LABEL: {{^}}same_base_ptr_crash:
28; SI: buffer_load_dword
29; SI: buffer_load_dword
30define void @same_base_ptr_crash(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) {
31entry:
32  %out1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
33  %tmp0 = load i32, i32 addrspace(1)* %out
34  %tmp1 = load i32, i32 addrspace(1)* %out1
35  %tmp2 = add i32 %tmp0, %tmp1
36  store i32 %tmp2, i32 addrspace(1)* %out
37  ret void
38}
39
40attributes #0 = { nounwind }
41attributes #1 = { nounwind readnone }
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