source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/AMDGPU/zero_extend.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.2 KB
Line 
1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
2; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI
3; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI
4
5; R600: {{^}}test:
6; R600: MEM_RAT_CACHELESS STORE_RAW
7; R600: MEM_RAT_CACHELESS STORE_RAW
8
9; SI: {{^}}test:
10; SI: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
11; SI: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}}
12define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
13entry:
14  %0 = mul i32 %a, %b
15  %1 = add i32 %0, %c
16  %2 = zext i32 %1 to i64
17  store i64 %2, i64 addrspace(1)* %out
18  ret void
19}
20
21; SI-LABEL: {{^}}testi1toi32:
22; SI: v_cndmask_b32
23define void @testi1toi32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
24entry:
25  %0 = icmp eq i32 %a, %b
26  %1 = zext i1 %0 to i32
27  store i32 %1, i32 addrspace(1)* %out
28  ret void
29}
30
31; SI-LABEL: {{^}}zext_i1_to_i64:
32; SI: s_mov_b32 s{{[0-9]+}}, 0
33; SI: v_cmp_eq_i32
34; SI: v_cndmask_b32
35define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
36  %cmp = icmp eq i32 %a, %b
37  %ext = zext i1 %cmp to i64
38  store i64 %ext, i64 addrspace(1)* %out, align 8
39  ret void
40}
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