source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.3 KB
Line 
1; RUN: llc < %s -march=arm -mattr=+neon
2; PR4657
3
4target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
5target triple = "armv7-apple-darwin9"
6
7define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
8entry:
9        %v_addr = alloca <4 x i32>              ; <<4 x i32>*> [#uses=2]
10        %f_addr = alloca i32            ; <i32*> [#uses=2]
11        %retval = alloca <4 x i32>              ; <<4 x i32>*> [#uses=2]
12        %0 = alloca <4 x i32>           ; <<4 x i32>*> [#uses=2]
13        %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
14        store <4 x i32> %v, <4 x i32>* %v_addr
15        store i32 %f, i32* %f_addr
16        %1 = load <4 x i32>, <4 x i32>* %v_addr, align 16               ; <<4 x i32>> [#uses=1]
17        %2 = load i32, i32* %f_addr, align 4            ; <i32> [#uses=1]
18        %3 = insertelement <4 x i32> undef, i32 %2, i32 0               ; <<4 x i32>> [#uses=1]
19        %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer             ; <<4 x i32>> [#uses=1]
20        %5 = mul <4 x i32> %1, %4               ; <<4 x i32>> [#uses=1]
21        store <4 x i32> %5, <4 x i32>* %0, align 16
22        %6 = load <4 x i32>, <4 x i32>* %0, align 16            ; <<4 x i32>> [#uses=1]
23        store <4 x i32> %6, <4 x i32>* %retval, align 16
24        br label %return
25
26return:         ; preds = %entry
27        %retval1 = load <4 x i32>, <4 x i32>* %retval           ; <<4 x i32>> [#uses=1]
28        ret <4 x i32> %retval1
29}
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