source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.8 KB
Line 
1; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null
2
3define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
4  %1 = ptrtoint i8* %pBuffer to i32
5
6  %lsr.iv2641 = inttoptr i32 %1 to float*
7  %tmp29 = add i32 %1, 4
8  %tmp2930 = inttoptr i32 %tmp29 to float*
9  %tmp31 = add i32 %1, 8
10  %tmp3132 = inttoptr i32 %tmp31 to float*
11  %tmp33 = add i32 %1, 12
12  %tmp3334 = inttoptr i32 %tmp33 to float*
13  %tmp35 = add i32 %1, 16
14  %tmp3536 = inttoptr i32 %tmp35 to float*
15  %tmp37 = add i32 %1, 20
16  %tmp3738 = inttoptr i32 %tmp37 to float*
17  %tmp39 = add i32 %1, 24
18  %tmp3940 = inttoptr i32 %tmp39 to float*
19  %2 = load float, float* %lsr.iv2641, align 4
20  %3 = load float, float* %tmp2930, align 4
21  %4 = load float, float* %tmp3132, align 4
22  %5 = load float, float* %tmp3334, align 4
23  %6 = load float, float* %tmp3536, align 4
24  %7 = load float, float* %tmp3738, align 4
25  %8 = load float, float* %tmp3940, align 4
26  %9 = insertelement <4 x float> undef, float %6, i32 0
27  %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
28  %11 = insertelement <4 x float> %10, float %7, i32 1
29  %12 = insertelement <4 x float> %11, float %8, i32 2
30  %13 = insertelement <4 x float> undef, float %2, i32 0
31  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> zeroinitializer
32  %15 = insertelement <4 x float> %14, float %3, i32 1
33  %16 = insertelement <4 x float> %15, float %4, i32 2
34  %17 = insertelement <4 x float> %16, float %5, i32 3
35  %18 = fsub <4 x float> zeroinitializer, %12
36  %19 = shufflevector <4 x float> %18, <4 x float> undef, <4 x i32> zeroinitializer
37  %20 = shufflevector <4 x float> %17, <4 x float> undef, <2 x i32> <i32 0, i32 1>
38  %21 = shufflevector <2 x float> %20, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
39
40  ret <4 x float> %21
41}
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