source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs
2; PR11829
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
4target triple = "armv7-none-linux-gnueabi"
5
6define arm_aapcs_vfpcc void @foo(i8* nocapture %arg) nounwind uwtable align 2 {
7bb:
8  br i1 undef, label %bb1, label %bb2
9
10bb1:                                              ; preds = %bb
11  unreachable
12
13bb2:                                              ; preds = %bb
14  br label %bb3
15
16bb3:                                              ; preds = %bb4, %bb2
17  %tmp = icmp slt i32 undef, undef
18  br i1 %tmp, label %bb4, label %bb67
19
20bb4:                                              ; preds = %bb3
21  %tmp5 = load <4 x i32>, <4 x i32>* undef, align 16
22  %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
23  %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
24  %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
25  %tmp9 = fsub <4 x float> %tmp8, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
26  %tmp10 = fmul <4 x float> undef, %tmp9
27  %tmp11 = fadd <4 x float> undef, %tmp10
28  %tmp12 = bitcast <4 x float> zeroinitializer to i128
29  %tmp13 = lshr i128 %tmp12, 64
30  %tmp14 = trunc i128 %tmp13 to i64
31  %tmp15 = insertvalue [2 x i64] undef, i64 %tmp14, 1
32  %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
33  %tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) nounwind
34  %tmp18 = fmul <4 x float> %tmp17, %tmp16
35  %tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) nounwind
36  %tmp20 = fmul <4 x float> %tmp19, %tmp18
37  %tmp21 = fmul <4 x float> %tmp20, zeroinitializer
38  %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind
39  call arm_aapcs_vfpcc  void @bar(i8* null, i8* undef, <4 x i32>* undef, [2 x i64] zeroinitializer) nounwind
40  %tmp23 = bitcast <4 x float> %tmp22 to i128
41  %tmp24 = trunc i128 %tmp23 to i64
42  %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
43  %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
44  %tmp27 = load float, float* undef, align 4
45  %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
46  %tmp29 = load <4 x i32>, <4 x i32>* undef, align 16
47  %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
48  %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
49  %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
50  %tmp33 = fsub <4 x float> %tmp32, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
51  %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind
52  %tmp35 = fmul <4 x float> %tmp34, undef
53  %tmp36 = fmul <4 x float> %tmp35, undef
54  %tmp37 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
55  %tmp38 = load float, float* undef, align 4
56  %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
57  %tmp40 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
58  %tmp41 = load float, float* undef, align 4
59  %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
60  %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
61  %tmp44 = fmul <4 x float> %tmp33, %tmp43
62  %tmp45 = fadd <4 x float> %tmp42, %tmp44
63  %tmp46 = fsub <4 x float> %tmp45, undef
64  %tmp47 = fmul <4 x float> %tmp46, %tmp36
65  %tmp48 = fadd <4 x float> undef, %tmp47
66  %tmp49 = call arm_aapcs_vfpcc  i8* undef(i8* undef) nounwind
67  %tmp50 = load float, float* undef, align 4
68  %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
69  %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
70  %tmp54 = load float, float* %tmp52, align 4
71  %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
72  %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
73  %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
74  %tmp58 = fmul <4 x float> undef, %tmp57
75  %tmp59 = fsub <4 x float> %tmp51, %tmp48
76  %tmp60 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp58
77  %tmp61 = fmul <4 x float> %tmp59, %tmp60
78  %tmp62 = fadd <4 x float> %tmp48, %tmp61
79  call arm_aapcs_vfpcc  void @baz(i8* undef, i8* undef, [2 x i64] %tmp26, <4 x i32>* undef)
80  %tmp63 = bitcast <4 x float> %tmp62 to i128
81  %tmp64 = lshr i128 %tmp63, 64
82  %tmp65 = trunc i128 %tmp64 to i64
83  %tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1
84  call arm_aapcs_vfpcc  void @quux(i8* undef, i8* undef, [2 x i64] undef, i8* undef, [2 x i64] %tmp66, i8* undef, i8* undef, [2 x i64] %tmp26, [2 x i64] %tmp15, <4 x i32>* undef)
85  br label %bb3
86
87bb67:                                             ; preds = %bb3
88  ret void
89}
90
91declare arm_aapcs_vfpcc void @bar(i8*, i8*, <4 x i32>*, [2 x i64])
92
93declare arm_aapcs_vfpcc void @baz(i8*, i8* nocapture, [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
94
95declare arm_aapcs_vfpcc void @quux(i8*, i8*, [2 x i64], i8* nocapture, [2 x i64], i8* nocapture, i8* nocapture, [2 x i64], [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
96
97declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
98
99declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
100
101declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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