source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

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1; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
2; PR11841
3; PR11829
4target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
5target triple = "armv7-none-linux-eabi"
6
7; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
8define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
9bb:
10  %tmp = load <2 x float>, <2 x float>* undef, align 8
11  %tmp2 = extractelement <2 x float> %tmp, i32 0
12  %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
13  %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
14  %tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2
15  %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
16  %tmp7 = extractelement <2 x float> %tmp, i32 1
17  %tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1
18  %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2
19  %tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3
20  %tmp11 = bitcast <4 x float> %tmp6 to <2 x i64>
21  %tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer
22  %tmp13 = bitcast <1 x i64> %tmp12 to <2 x float>
23  %tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer
24  %tmp15 = bitcast <4 x float> %tmp14 to <2 x i64>
25  %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
26  %tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
27  %tmp18 = extractelement <2 x float> %tmp17, i32 0
28  tail call arm_aapcs_vfpcc  void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
29  %tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
30  %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
31  %tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
32  %tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
33  %tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
34  %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
35  %tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
36  %tmp26 = extractelement <2 x float> %tmp25, i32 0
37  tail call arm_aapcs_vfpcc  void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
38  ret void
39}
40
41define arm_aapcs_vfpcc void @foo2() nounwind uwtable {
42entry:
43  br i1 undef, label %for.end, label %cond.end295
44
45cond.end295:                                      ; preds = %entry
46  %shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
47  %shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
48  %shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32> <i32 0, i32 1>
49  %0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float>
50  %1 = bitcast <4 x float> undef to <2 x i64>
51  %shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
52  %shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
53  %shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> <i32 0, i32 1>
54  %2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float>
55  tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
56  tail call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
57  unreachable
58
59for.end:                                          ; preds = %entry
60  ret void
61}
62
63; Check that pseudo-expansion preserves <undef> flags.
64define void @foo3(i8* %p) nounwind ssp {
65entry:
66  tail call void @llvm.arm.neon.vst2.p0i8.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4)
67  ret void
68}
69
70declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
71declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind
72declare void @llvm.arm.neon.vst2.p0i8.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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