source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/2012-08-09-neon-extload.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

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Line 
1; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
2
3@var_v2i8 = global <2 x i8> zeroinitializer
4@var_v4i8 = global <4 x i8> zeroinitializer
5
6@var_v2i16 = global <2 x i16> zeroinitializer
7@var_v4i16 = global <4 x i16> zeroinitializer
8
9@var_v2i32 = global <2 x i32> zeroinitializer
10@var_v4i32 = global <4 x i32> zeroinitializer
11
12@var_v2i64 = global <2 x i64> zeroinitializer
13
14define void @test_v2i8tov2i32() {
15; CHECK-LABEL: test_v2i8tov2i32:
16
17  %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
18
19  %i32val = sext <2 x i8> %i8val to <2 x i32>
20  store <2 x i32> %i32val, <2 x i32>* @var_v2i32
21; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
23; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
24
25  ret void
26}
27
28define void @test_v2i8tov2i64() {
29; CHECK-LABEL: test_v2i8tov2i64:
30
31  %i8val = load <2 x i8>, <2 x i8>* @var_v2i8
32
33  %i64val = sext <2 x i8> %i8val to <2 x i64>
34  store <2 x i64> %i64val, <2 x i64>* @var_v2i64
35; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
36; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
37; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
38; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}}
39
40;  %i64val = sext <2 x i8> %i8val to <2 x i64>
41;  store <2 x i64> %i64val, <2 x i64>* @var_v2i64
42
43  ret void
44}
45
46define void @test_v4i8tov4i16() {
47; CHECK-LABEL: test_v4i8tov4i16:
48
49  %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
50
51  %i16val = sext <4 x i8> %i8val to <4 x i16>
52  store <4 x i16> %i16val, <4 x i16>* @var_v4i16
53; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
55; CHECK-NOT: vmovl.s16
56
57  ret void
58; CHECK: bx lr
59}
60
61define void @test_v4i8tov4i32() {
62; CHECK-LABEL: test_v4i8tov4i32:
63
64  %i8val = load <4 x i8>, <4 x i8>* @var_v4i8
65
66  %i16val = sext <4 x i8> %i8val to <4 x i32>
67  store <4 x i32> %i16val, <4 x i32>* @var_v4i32
68; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
70; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
71
72  ret void
73}
74
75define void @test_v2i16tov2i32() {
76; CHECK-LABEL: test_v2i16tov2i32:
77
78  %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
79
80  %i32val = sext <2 x i16> %i16val to <2 x i32>
81  store <2 x i32> %i32val, <2 x i32>* @var_v2i32
82; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
84; CHECK-NOT: vmovl
85
86  ret void
87; CHECK: bx lr
88}
89
90define void @test_v2i16tov2i64() {
91; CHECK-LABEL: test_v2i16tov2i64:
92
93  %i16val = load <2 x i16>, <2 x i16>* @var_v2i16
94
95  %i64val = sext <2 x i16> %i16val to <2 x i64>
96  store <2 x i64> %i64val, <2 x i64>* @var_v2i64
97; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
98; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
99; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]]
100
101  ret void
102}
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