1 | ; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \ |
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2 | ; RUN: | FileCheck %s |
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3 | |
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4 | ; This test checks that the VMLxForwarting feature is disabled for A15. |
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5 | ; CHECK: fun_a: |
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6 | define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{ |
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7 | %1 = add <4 x i32> %x, %y |
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8 | ; CHECK-NOT: vmul |
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9 | ; CHECK: vmla |
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10 | %2 = mul <4 x i32> %1, %1 |
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11 | %3 = add <4 x i32> %y, %2 |
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12 | ret <4 x i32> %3 |
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13 | } |
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14 | |
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15 | ; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting |
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16 | ; Cortex-A15. |
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17 | ; CHECK: fun_b: |
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18 | define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{ |
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19 | ; CHECK: vmla.f32 |
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20 | %t = fmul <4 x float> %x, %y |
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21 | %r = fadd <4 x float> %t, %z |
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22 | ret <4 x float> %r |
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23 | } |
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24 | |
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25 | ; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition |
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26 | ; operations when targeting Cortex-A15. |
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27 | ; CHECK: fun_c: |
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28 | define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{ |
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29 | ; CHECK: vmla.f32 |
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30 | %t1 = fmul <4 x float> %x, %y |
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31 | %r1 = fadd <4 x float> %t1, %z |
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32 | ; CHECK: vmla.f32 |
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33 | %t2 = fmul <4 x float> %u, %v |
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34 | %r2 = fadd <4 x float> %t2, %r1 |
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35 | ret <4 x float> %r2 |
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36 | } |
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37 | |
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