source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/a15-partial-update.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 1.3 KB
Line 
1; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s  | FileCheck %s
2
3; CHECK-LABEL: t1:
4define <2 x float> @t1(float* %A, <2 x float> %B) {
5; The generated code for this test uses a vld1.32 instruction
6; to write the lane 1 of a D register containing the value of
7; <2 x float> %B. Since the D register is defined, it would
8; be incorrect to fully write it (with a vmov.f64) before the
9; vld1.32 instruction. The test checks that a vmov.f64 was not
10; generated.
11
12; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}},
13  %tmp2 = load float, float* %A, align 4
14  %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1
15  ret <2 x float> %tmp3
16}
17
18; CHECK-LABEL: t2:
19define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
20entry:
21  br label %loop
22loop:
23; The code generated by this test uses a vld1.32 instruction.
24; We check that a dependency breaking vmov* instruction was
25; generated.
26
27; CHECK: vmov.{{.*}} d{{[0-9]+}},
28  %oldcount = phi i32 [0, %entry], [%newcount, %loop]
29  %newcount = add i32 %oldcount, 1
30  %p1 = getelementptr <4 x i8>, <4 x i8> *%in, i32 %newcount
31  %p2 = getelementptr <4 x i8>, <4 x i8> *%out, i32 %newcount
32  %tmp1 = load <4 x i8> , <4 x i8> *%p1, align 4
33  store <4 x i8> %tmp1, <4 x i8> *%p2
34  %cmp = icmp eq i32 %newcount, %n
35  br i1 %cmp, label %loop, label %ret
36ret:
37  ret void
38}
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