source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/fast-isel-pic.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

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1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
3; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -arm-force-fast-isel -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
4; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -arm-force-fast-isel -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
5
6@g = global i32 0, align 4
7
8define i32 @LoadGV() {
9entry:
10; THUMB: LoadGV
11; THUMB: movw [[reg0:r[0-9]+]],
12; THUMB: movt [[reg0]],
13; THUMB: add  [[reg0]], pc
14; THUMB-ELF: LoadGV
15; THUMB-ELF: ldr r[[reg0:[0-9]+]],
16; THUMB-ELF: add r[[reg0]], pc
17; THUMB-ELF: ldr r[[reg0]], [r[[reg0]]]
18; ARM: LoadGV
19; ARM: ldr [[reg1:r[0-9]+]],
20; ARM: add [[reg1]], pc, [[reg1]]
21; ARMv7: LoadGV
22; ARMv7: movw [[reg2:r[0-9]+]],
23; ARMv7: movt [[reg2]],
24; ARMv7: add  [[reg2]], pc, [[reg2]]
25; ARMv7-ELF: LoadGV
26; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
27; ARMv7-ELF: .LPC
28; ARMv7-ELF-NEXT: ldr r[[reg2]], [pc, r[[reg2]]]
29; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]]]
30  %tmp = load i32, i32* @g
31  ret i32 %tmp
32}
33
34@i = external global i32
35
36define i32 @LoadIndirectSymbol() {
37entry:
38; THUMB: LoadIndirectSymbol
39; THUMB: movw r[[reg3:[0-9]+]],
40; THUMB: movt r[[reg3]],
41; THUMB: add  r[[reg3]], pc
42; THUMB: ldr  r[[reg3]], [r[[reg3]]]
43; THUMB-ELF: LoadIndirectSymbol
44; THUMB-ELF: ldr r[[reg3:[0-9]+]],
45; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46; THUMB-ELF: ldr r0, [r[[reg4]]]
47; ARM: LoadIndirectSymbol
48; ARM: ldr [[reg4:r[0-9]+]],
49; ARM: ldr [[reg4]], [pc, [[reg4]]]
50; ARMv7: LoadIndirectSymbol
51; ARMv7: movw r[[reg5:[0-9]+]],
52; ARMv7: movt r[[reg5]],
53; ARMv7: add  r[[reg5]], pc, r[[reg5]]
54; ARMv7: ldr  r[[reg5]], [r[[reg5]]]
55; ARMv7-ELF: LoadIndirectSymbol
56; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
57; ARMv7-ELF: .LPC
58; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]]
59; ARMv7-ELF: ldr r0, [r[[reg5]]]
60  %tmp = load i32, i32* @i
61  ret i32 %tmp
62}
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