source: icGREP/icgrep-devel/llvm-3.8.0.src/test/CodeGen/ARM/intrinsics-crypto.ll @ 5027

Last change on this file since 5027 was 5027, checked in by cameron, 3 years ago

Upgrade to llvm 3.8

File size: 3.3 KB
Line 
1; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
2
3define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
4  %tmp = load <16 x i8>, <16 x i8>* %a
5  %tmp2 = load <16 x i8>, <16 x i8>* %b
6  %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
7  ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
8  %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
9  ; CHECK: aese.8 q{{[0-9]+}}, q{{[0-9]+}}
10  %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4)
11  ; CHECK: aesimc.8 q{{[0-9]+}}, q{{[0-9]+}}
12  %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5)
13  ; CHECK: aesmc.8 q{{[0-9]+}}, q{{[0-9]+}}
14  ret <16 x i8> %tmp6
15}
16
17define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
18  %tmp = load <4 x i32>, <4 x i32>* %a
19  %tmp2 = load <4 x i32>, <4 x i32>* %b
20  %tmp3 = load <4 x i32>, <4 x i32>* %c
21  %scalar = extractelement <4 x i32> %tmp, i32 0
22  %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
23  %res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0
24  ; CHECK: sha1h.32 q{{[0-9]+}}, q{{[0-9]+}}
25  %res2 = call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %tmp2, i32 %scalar, <4 x i32> %res1)
26  ; CHECK: sha1c.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
27  %res3 = call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %res2, i32 %scalar, <4 x i32> %res1)
28  ; CHECK: sha1m.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
29  %res4 = call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %res3, i32 %scalar, <4 x i32> %res1)
30  ; CHECK: sha1p.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
31  %res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
32  ; CHECK: sha1su0.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
33  %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
34  ; CHECK: sha1su1.32 q{{[0-9]+}}, q{{[0-9]+}}
35  %res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
36  ; CHECK: sha256h.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
37  %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
38  ; CHECK: sha256h2.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
39  %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
40  ; CHECK: sha256su1.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
41  %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
42  ; CHECK: sha256su0.32 q{{[0-9]+}}, q{{[0-9]+}}
43  ret <4 x i32> %res10
44}
45
46declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>)
47declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>)
48declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>)
49declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>)
50declare i32 @llvm.arm.neon.sha1h(i32)
51declare <4 x i32> @llvm.arm.neon.sha1c(<4 x i32>, i32, <4 x i32>)
52declare <4 x i32> @llvm.arm.neon.sha1m(<4 x i32>, i32, <4 x i32>)
53declare <4 x i32> @llvm.arm.neon.sha1p(<4 x i32>, i32, <4 x i32>)
54declare <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32>, <4 x i32>, <4 x i32>)
55declare <4 x i32> @llvm.arm.neon.sha256h(<4 x i32>, <4 x i32>, <4 x i32>)
56declare <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32>, <4 x i32>, <4 x i32>)
57declare <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>)
58declare <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32>, <4 x i32>)
59declare <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32>, <4 x i32>)
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